Semiconductor integrated circuit

ABSTRACT

In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of U.S. patent application Ser.No. 09/375,370, filed Aug. 17, 1999, which is based upon and claims thebenefit of priority from the prior Japanese Patent Application No.10-230478, filed Aug. 17, 1998, the entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a semiconductor integratedcircuit and particularly, to a configuration and layout of a powersupply circuit of the semiconductor integrated circuit which prevents amalfunction in a semiconductor integrated circuit caused by a transientchange in power supply voltage when a power supply is turned on fromoccurring and suppresses a decrease in internal power supply voltageimmediately after a transition from a stand-by mode to an active mode.

[0003] Conventionally, a power-on circuit has been known as a powersupply voltage detecting circuit which generates a signal by detectingan increase and a decrease in power supply. When a power supply isturned on, a power supply voltage is increased and exceeds a presetvalue, a detection signal is generated and a prescribed latch in asemiconductor integrated circuit is reset to a required initial stateusing the signal. On the other hand, when a power supply voltage isdecreased and reaches a preset value, a detection signal is generated, aprescribed latch is reset as in when a power supply is turned on. Then,description will be given of a necessity of resetting of a prescribedlatch when a power supply voltage is decreased, taking a non-volatilememory having a floating gate as example.

[0004] A sectional view of a structure of a non-volatile memory cell isshown in FIG. 26. Cells 1 and 2 are formed on a silicon substrate,wherein a control gate 40 and a floating gate 41 are provided to each ofthe cells 1 and 2, channels are formed on the surface of a P well 42 andN-type diffusion layers 43 formed on the P well 42 are respectively usedas a source and a drain.

[0005] A write operation of the non-volatile memory cell is effected byapplying a high voltage of the order of 20V between the control gate 40and the P well 42 with the control gate 40 being set positive. At thispoint, electrons are injected into the floating gate 41 from the P well42 and the memory cell is in a written state.

[0006] Then, an erase operation is effected by applying a high voltageof the order of 20V between the control gate 40 and the P well 42 with apotential of the control gate 40 being set 0 or negative, contrary tothe write operation, to draw back the electrons in the floating gate 41injected in the write operation to the P well 42. A situation in whichthe cell 1 is erased is shown in FIG. 26.

[0007] That is, for example, when the cell 1 is selected on theassumption that the cells 1 and 2 of FIG. 26 each are in a written stateand if the control gate 40 and the P well are respectively applied with0V and 20V, electrons (e⁻) injected in the floating gate 41 are drawnback to the P well 42 by a tunnel effect to have the cell 1 to be anerased state.

[0008] At this point, the control gate 40 is applied with 20V in anon-selected cell 2 and no potential difference between the floatinggate 41 and the P well 42 arises. Therefore, electrons injected in thefloating gate 41 of the cell 2 are retained.

[0009] However, in a case where a power supply voltage is decreased inthe erase operation for some reason, a logic circuit malfunctions due tothe voltage decrease and in turn, a voltage of the control gate 40 ofthe cell 2 is decreased to 0V although the voltage should normally beapplied with 20V. With the decrease in the voltage, electrons in thefloating gate 41 of the cell 2 which should normally be retained aredrawn back to the P well 42, thereby effecting an erroneous eraseoperation.

[0010] In order to prevent such a malfunction, it is indispensable thata decrease in power supply voltage is detected immediately when itarises and a potential of the P well 42 be decreased from 20V to 0V. Apower-on signal to be generated when the power supply voltage isdecreased is necessary for such a recovery operation.

[0011] Conventionally, as a circuit which generates a power-on signal, apower supply voltage detecting circuit as shown in FIG. 27 has beenemployed. The power supply voltage detecting circuit of FIG. 27 isconstructed of: a power supply; resistors R1, R2 and R3; an N channelMOS transistor (hereinafter referred to as NMOS) M1 with a thresholdvoltage Vtn; a P channel MOS transistor (hereinafter referred to asPMOS) M2 with a threshold voltage Vtp; a node N1 connecting a connectionpoint between the resistors R1 and R2 and the gate of PMOS (M2) witheach other; a node N2 connecting the drain of PMOS (M2) and the resistorR3; and two inverters 15 and 16 connected to the output side. A powersupply voltage and a voltage of the node N1 when a power supply isturned on are respectively denoted by V and VN1, then VN1 is given asfollows:

VN1=R1×Vtn/(R1+R2)+R2×V/(R1+R2)  (1)

[0012] In a case where, when a power supply is turned on, a differencebetween V and VN1 exceeds the absolute value |Vtp| of a thresholdvoltage of PMOS (M2), that is, when the power supply voltage is higherthan Vpwon, which is expressed as follows:

Vpwon=Vtn+|Vtp|×(R1+R2)/R1  (2)

[0013] a potential of the node N2 goes to high level (hereinafterexpressed as “H”) and an output of the power-supply detecting circuitchanges to “H” from a low level (hereinafter referred to as “L”). Withthis operation adopted, a prescribed latch in a semiconductor integratedcircuit can be reset. When a power supply voltage is decreased andreaches the level of the equation (2), the output changes from “H” to“L” and the prescribed latch can be reset.

[0014] Incidentally, in FIG. 27, the gate and drain of NMOS (M1) areconnected with each other and used as an NMOS connected as a diode.Further, the resistor R2 may be removed in the circuit shown in FIG. 27since no problem occurs even if the resistance R2=0 in the equations (1)and (2).

[0015] The power supply voltage detecting circuit is employed in acircuit system in which no down converter is provided. In a circuitsystem in which an external power supply voltage Vext is decreased to aninternal power supply voltage Vint using a down converter, aconfiguration and function of the power supply voltage detecting circuitis more or less altered.

[0016] The down converter system used herein (see “Super LSI memory,”authored by Shizuo ITO published by BAIFU KAN, p 267) is a circuitsystem in which Vext (for example, 3V) which is supplied from theoutside of a semiconductor chip is decreased to Vint (for example, 2.5V)using a down converter and the Vint is used as a power supply for aninternal circuit in the semiconductor integrated circuit.

[0017] A down converter system is especially widely used insemiconductor integrated circuits such as a memory and is useful as avery effective measure to cope with reduction in breakdown voltage of atransistor used in an internal circuit, which accompanies progress inmicrofabrication technique, and further, becomes an important measure tosupport a trend toward a multiple power supply for a semiconductorintegrated circuit.

[0018] In a down converter system, two kinds of power supply detectingcircuits for Vext and Vint are required. A Vext detecting circuitdetects an increase in Vext and activates a down converter and areference voltage (hereinafter referred to as Vref) generating circuit,while, when Vext is decreased, the circuit provides a function similarto a conventional manner.

[0019] A Vint detecting circuit further functions to reset a latch to arequired initial condition in an increase in Vint as in a conventionalmanner when a power supply is turned on. However, when Vint isdecreased, the Vint detecting circuit is not required to output asignal. The reason why is that the Vext detecting circuit detects adecrease in external power supply voltage prior to a decrease ininternal power supply voltage Vint.

[0020] If functions of the Vext and Vint detecting circuits areconsidered, it is understood that a detecting circuit which outputssignals when a power supply voltage reaches the same voltage level inboth cases of an increase and a decrease in power supply voltage may beadopted as a Vext detecting circuit as in a conventional manner. On theother hand, if such a circuit is adopted as a Vint detecting circuit, aproblem which will be described below arises.

[0021] While Vint in a down converter system is generated by decreasingVext using a down converter, characteristics of the down converter are,in the case, required to be determined so that a voltage level of Vintis constant regardless of a magnitude of Vext and an amount of a currentconsumption of an internal circuit.

[0022] However, when a lot of current is consumed in a short time in theinternal circuit, an instantaneous decrease in voltage level Vint cannotbe prevented from occurring. Such a situation occurs, for example, incases where an extremely large capacitance is charged from 0V to Vint involtage level and data are inverted in a number of latches at almost thesame point of time, whereby a lot of current flows through circuits inan instant, and the like case. The term “current flowing throughcircuits” is that while a power supply current is normally interruptedin the course of inversion of a CMOS gate, the current flows through inan unexpected instant.

[0023] Once the Vint detecting circuit detects such a temporary decreasein Vint, there arises a problem that a latch in which importantinformation such as an address, written data in a memory cell is storedis reset to an initial state.

[0024] Incidentally, as described above, while a down converterdecreases Vext and generates Vint and consumes a current constantly inorder to keep Vint at a constant level, an amount of the currentconsumption is different according to an ability of the down converter(an ability to keep Vint at a constant level) and as the ability ishigher, the current consumption is increased.

[0025] In order to suppress power consumption in the down converter aslow as possible, there have been proposed various kinds of systems inwhich an internal circuit is respectively operated according to twocases: one case in an active mode where a large current is consumed andthereby, a high ability is required for the circuit and the other in astand-by mode where almost no current flows through an internal circuit(see “Super LSI memory,” authored by Shizuo ITO published by BAIFU KAN,pp. 307 to 310).

[0026]FIG. 28 conceptually shows a configuration in which an internalcircuit is differently operated according to cases. While a stand-bymode down converter 9 whose power consumption is low is constantlyoperated, an active mode down converter 10 whose power consumption ishigh is operated only in an active mode. In a conventional example shownin FIG. 28, Vint of the stand-by mode down converter 9 and Vint of theactive mode down converter 10 are both set to the same voltage level.

[0027] A conventional active mode down converter 10 is a circuit with ahigh speed response in order to suppress a fluctuation in Vint. However,a time period is required from when an enable signal generating section7 of an active mode down converter outputs an enable signal till theactive mode down converter 10 reaches an operating state. When, duringsuch a time period, an internal circuit 11 consumes a large current,there arises a problem that the stand-by mode down converter 9 cannotsingly suppress fluctuations in Vint and thereby Vint is decreased. Thedecrease in Vint is about 0.2V.

[0028] Then, the reason why a power supply for a chip is required toadopt a multiple power supply system such as in the case of acombination of Vext and Vint and down converters which haveconventionally been studied will be described in a more detailed mannerof the case of a semiconductor integrated circuit such as a memory ascentral issues.

[0029] According to a scaling rule of a transistor, when a size of atransistor is reduced to 1/K of the original size, a magnitude of apower supply voltage is also required to be 1/K of the original voltage,in order to operate a transistor under the same electric field strength.Actually, however, the power supply voltage cannot freely be changedsince the voltage is dependent on systems which are incorporated in achip.

[0030] Hence, it has often been conducted that only sizes of transistorsare reduced while a magnitude of a power supply voltage of the precedinggeneration is maintained. In this case, a power supply voltage isdecreased on a chip and such a decreased voltage is applied tominiaturized transistors in use for an internal circuit in order that animmunity to the hot-electron effect of the transistors is notproblematic in practical aspects.

[0031] In a concrete manner of description, while it is desirable fromthe viewpoint of high integration and realization of a high speed that agate oxide film of an MOS transistor is thinned in a semiconductorintegrated circuit of a memory such as DRAM or a non-volatile memory,there arise problems of reliability such as dielectric breakdown of thegate oxide film, reduction in hot electron resistance if the gate oxidefilm is only thinned without any decrease in the power supply voltage.

[0032] When a gate length of an MOS transistor is shortened and thereby,an electric field strength in the drain region is increased,electrons/holes which are accelerated in the drain region become a highenergy state and are injected into a gate oxide film or the like, whichresults in deterioration of characteristics of the MOS transistor. Thehot electron resistance herein is an ability whereby the transistorendures such a phenomenon.

[0033] Accordingly, when a thin oxide film is used, it is indispensablethat a power supply voltage is decreased and the hot electron resistanceis improved, but there is existent an MOS transistor with a thick gateoxide film which does not require reduction in power supply voltage in aCPU and the like, which are in a mixed manner formed on the same chiptogether with the DRAM, a non-volatile memory or the like, and whichshare the same power-supply. A power supply voltage for an MOStransistor in such a CPU and the like are not desired to be reducedtogether with a collective reduction in power supply voltage of theentire system since the reduction results in a decreased operating speedof the system.

[0034] For this reason, a down converter system is effective in whichVext supplied from the outside of a semiconductor integrated circuit isdecreased and thus decreased voltage is used as Vint for an internalcircuit. The voltage-decreasing system has heretofore been employedmainly for DRAM. As a down converter for Vext in this case, thefollowing two kinds have been known mainly.

[0035] One is a circuit which decreases a voltage through PMOS and acircuit configuration is shown in FIG. 29. The down converter is,hereinafter, referred to as PMOS type. As shown in FIG. 29, the PMOSdown converter constitutes a feed-back system and a gate voltage of PMOS(M18) is to be determined according to a value of Vint.

[0036] That is, if Vint (a power supply voltage VDD of an internalcircuit) is decreased, thus decreased Vint is detected from comparisonof a voltage obtained by resistance division of Vint between resistorsR15 and R16, with Vref and a gate voltage of the PMOS (M18) isdecreased. With the decrease in the gate voltage, Vint is increased. Tothe contrary, as Vint is increased, a gate voltage of the PMOS isincreased and since a supply current is suppressed, an increase in Vintis restricted. Incidentally, C4 is a capacitor for stabilization and C6is a capacitor for phase compensation in FIG. 29.

[0037] The other is a circuit which decreases a voltage through NMOS anda configuration thereof is shown in FIG. 30. The down converter is,hereinafter, referred to as NMOS type. An NMOS down converter does notconstitute a feed-back system and a gate voltage of the NMOS (M10) iskept at the sum of Vint (VDD) and a threshold voltage Vt of the NMOS byvoltage generating circuit constructed of a voltage limiter 13 and acharge pump circuit 14. If Vint is decreased, a potential differencebetween the gate and source of the NMOS (M10) is increased and thereby,a supply current is increased, so that Vint is increased. Incidentally,VDDH is an output voltage of voltage generating circuit, CDDH is acapacitor for stabilization of the output voltage and CDD is a capacitorfor stabilization of Vint (VDD).

[0038] As shown in FIG. 31, in an NMOS down converter, avoltage-decreasing MOS (M10 of FIG. 30) is operated in a sub-thresholdregion. This is because a fluctuation in internal voltage can besuppressed small even if current consumption of the internal circuit isfluctuated over several orders of magnitude. The sub-threshold regionherein means a operating region of a MOS transistor in which a smallerdrain current flows compared with in a normal operation in a case wherea gate is equal to or lower than a threshold voltage.

[0039] Voltages applied to electrodes and a current of avoltage-decreasing NMOS (M10) used in the NMOS down converter of FIG. 30are shown in FIG. 31A. Vext is applied to the drain of NMOS, Vint to thesource thereof and an output voltage VDDH of a voltage generatingcircuit to the gate thereof. That is, a drain voltage VD=Vext−Vint isapplied between the source and drain and a drain current ID flowstherethrough. A dependency of the drain current ID on the drain voltageVD is shown in FIG. 31B. The relation can be explained using amathematical expression as follows.

[0040] When a gate voltage of NMOS is denoted by VDDH, a thresholdvoltage by Vt, an electron charge by q, Boltsmann constant by k, anabsolute temperature by T, a drain current ID in the sub-thresholdregion of NMOS when a drain voltage is VD is expressed with a constantIO and n in the following way:

ID=IOexp [q(VDDH−Vt−VD)/nkT]  (3)

[0041] As can be understood from the above equation, a change in VD(corresponding to a change in internal power supply voltage Vint) isproportional to a value of log (ID/IO) and is limited to be small evenwhen a supply current ID is changed over several orders of magnitude(see FIG. 31B).

[0042] Further, while, as the voltage-decreasing NMOS, a transistor ofthe same kind as NMOS in use for an ordinary circuit is used, a gatewidth W of NMOS is required to be very large, for example, 100 mm,since, in the case of the voltage-decreasing NMOS, not only is theoperation effected in a sub-threshold region and a large supply currentis required to be secured. In the equation (3), increase in a gate widthW corresponds with increase in factor IO.

[0043] When the NMOS down converter shown in FIG. 30 is used, capacitorsfor voltage stabilization are required to be connected to terminals ofthe internal power supply voltage Vint and the gate voltage VDDH ofNMOS. A capacitor CDD connected to Vint (VDD) functions to compensate aninstantaneous decrease in Vint due to power consumption of a circuit. IfCDD is large, a decrease in Vint is small. On the other hand, acapacitor CDDH connected to the gate voltage VDHH of NMOS works forprevention of a fluctuation of the gate voltage from occurring incooperation with capacitive coupling in a channel section and acapacitance between interconnections.

[0044] A magnitude of CDDH is determined in consideration of a responsetime of a system including a voltage limiter 13 and a charge pumpcircuit 14. That is, if a time period from when the voltage limiter 13detects a decrease in VDDH till the charge pump circuit 14 restores adecreased voltage to the original voltage is short, a capacitance of thecapacitor CDDH connected to the terminal of VDDH may be small, but if itis long, a large capacitance of CDDH has to be connected in order tocompensate a decrease in VDDH during the time period.

[0045] While the two kinds of configurations of conventional downconverters have been available, some devices are required according tocharacteristics of both in actual phases. What is especially required tobe careful is operations of a down converter in operating modes,stand-by and active, of a semiconductor integrated circuit.

[0046] In a stand-by mode, not only current consumption of an internalcircuit but also current consumption of the down converter itself arerequired to be small in order to suppress total current consumption ofthe entire chip. To the contrary, response of the down converter may beslow.

[0047] On the other hand, in an active mode, as the current consumptionof the internal circuit is increased, an instantaneous increase/decreasein current consumption is unavoidable in accordance to an operatingmode. The down converter is required to function to constantly keep theinternal power supply voltage Vint at a prescribed level in a quickresponse to such an increase/decrease in current consumption.

[0048] When the PMOS down converter of FIG. 29 is used, there have beenproposed various kinds of systems in which down converters aredifferently operated according to an active mode or a stand-by mode inorder to meet the requirements as described above.

[0049]FIG. 32 conceptually shows a configuration in which such differentoperating modes of down converters are selected. A PMOS down converterwhich is of low power consumption but slow in response and a PMOS downconverter which is of high power consumption, but fast in responseconstitute a voltage-decreasing system, wherein in a stand-by mode, thePMOS stand-by mode down converter 9 a which is of low power consumptionis only operated according to an enable signal, while in an active mode,the PMOS active mode down converter 9 b which is fast in response isadditionally operated according to an enable signal. In the mean time,in the conventional example shown in FIG. 32, an internal power supplyvoltage of the stand-by mode down converter and an internal power supplyvoltage of the active mode down converter are set to the same level.

[0050] On the other hand, when the NMOS down converter of FIG. 30 isused, two kinds of circuits are not operated selectively according tothe stand-by mode or the active mode. That is, one NMOS down converteris continued to be always operated regardless of the stand-by mode orthe active mode. In this case, in order to suppress a stand-by current,it is required to suppress current consumption of voltage generatingcircuit including the voltage limiter 13 and the charge pump circuit 14.

[0051] As a result, while a response speed of a feed-back systemincluding the voltage limiter 13 and the charge pump circuit 14 islowered, such a lowered response speed is not problematic since afluctuation in voltage VDDH is small if a value of the capacitance ofCDDH for stabilization is set large.

[0052] Outlines of the conventional NMOS down converters and the PMOSdown converter have been described above. If down converters areselectively operated differently according to the stand-by mode or theactive mode in a down converter system, no problems arise in bothvoltage circuits, as far as a capability and power consumption of eachof the down converters are concerned. However, the down convertersrespectively have problems in circuit design and layout as describedbelow. Then the problems will be described individually.

[0053] Since current consumption of a PMOS down converter can be smallby using resistors R15 and R16 of high resistance of FIG. 29, thecircuit is suitable for a stand-by mode. However, since the circuitconstitutes a feed-back system, an internal power supply voltage Vintfalls in an oscillating state or a decrease in the voltage occurs ifdesign parameters such as phase compensation of a comparator constitutedof a differential amplifier and the like are not correctly estimated.Especially, it is very difficult to design a down converter which isoperated in a stand-by mode so that the circuit does not oscillate evenwhen the circuit is operated in an operating mode in which a current isincreased by 4 to 5 orders of magnitude.

[0054] That is, the PMOS down converter is easier to cause abnormalityin an active mode in which increase or decrease in current consumptionis more large than in a stand-by mode in which current consumption of aninternal circuit is small. In this case, in order to design a feed-backsystem in a secured manner, it is required that current consumption ofan internal circuit in each operating mode is correctly estimated andfurthermore, simulations in various conditions are executeddeliberately. Accordingly, a PMOS down converter has a high degree ofdifficulty in design and consumes a long design time compared with anNMOS down converter.

[0055] On the other hand, an NMOS down converter is easier to be usedthan a PMOS down converter in an operating state in which a largecurrent is consumed. However, while the NMOS down converter has anadvantage of easy design, it is hard to suppress current consumption ofthe down converter itself since control is effected by a charge pumpcircuit.

[0056] Further, the NMOS down converter has a disadvantage that thecircuit requires a large layout area. That is, the NMOS down convertercomprises the following elements:

[0057] (1) a capacitor CDD connected to an internal power supply;

[0058] (2) a capacitor CDDH connected to VDDH;

[0059] (3) a voltage-decreasing NMOS transistor; and

[0060] (4) VDDH voltage generating circuit (a charge pump circuit and alimiter)

[0061] and a layout area for each element is increased in the order from(1) to (4).

[0062] Why (1) and (2) occupies larger areas is that the elements eachrequire a capacitance of the order of nanofarads (nF) in order tostabilize a voltage. In the case of DRAM, the capacitors can beconstituted of those in the same shape as a memory cell. The capacitorsin the same shape as a memory cell are very much small in layout areaper a unit capacitance compared with an ordinary MOS capacitor.

[0063] Hence, in DRAM, restriction on a layout area caused by the (1)and (2) is comparatively small. However, when an NMOS capacitor isapplied to a semiconductor integrated circuit, for example anon-volatile memory, which does not include proper capacitive deviceslike DRAM, a very large layout area is required compared with the caseof DRAM since the capacitors of (1) and (2) are formed by ordinary MOScapacitors.

[0064] Further, when the capacitors are formed by MOS capacitors, acapacitor CDD of (1) is not problematic in reliability of an oxide filmsince a potential difference applied to both ends of an oxide film is ofthe order of an internal power supply voltage Vint (VDD), but acapacitor CDDH of (2) cannot use a MOS capacitor for CDD as it is fromthe viewpoint of reliability since a potential difference between bothends of an oxide film is large: VDDH=VDD+Vt (Vt is a threshold voltageof a voltage-decreasing NMOS).

[0065] Hence, as a capacitor CDDH of (2), a MOS capacitor, whose oxidefilm is thick, and whose breakdown voltage is large, has to be adoptedand therefore, a layout area for a capacitor is further increased.

[0066] Besides, in the NMOS down converter shown in FIG. 30, Vint (VDD)which is generated in the source of a voltage-decreasing NMOS transistor(M10) is supplied to peripheral circuits blocks. At this point, if adistance between the voltage-decreasing NMOS (M10) and the peripheralcircuit blocks are too much, interconnection therebetween is a cause toprovide unintentional parasitic resistance. In a down converter, controlis effected so that the source of a voltage-decreasing NMOS (M10) is ata constant voltage and therefore, VDD is decreased due to the parasiticresistance in the peripheral circuit block.

[0067] Further, in an NMOS down converter, though it is preferable thata uniform operation is effected over the whole of a large gate width ofthe voltage-decreasing NMOS (M10), if a layout area of thevoltage-decreasing NMOS is too large, a part of the gate width W has achance to get early operated compared with the other parts due to aparasitic resistance of interconnection which is connected with thevoltage-decreasing NMOS (M10). Therefore, it is required that a layoutarea of the NMOS down converter is contracted and thereby the length ofinterconnection is suppressed, as a result decreasing parasiticresistance of interconnection.

[0068] However, in a memory such as a NAND flash memory (abatch-erasable memory), there is an operation in which a very largecapacitance including those of word lines, a power supply node in asense amplifier is charged in one time and at this operation, a largecurrent flows locally. For example, in data write, a current whichcharges word line capacitance of the order of 60 nF flows in a wordlinedriver circuit in a concentrated manner. In order to suppress afluctuation in operation of a voltage-decreasing NMOS (M10) due to sucha transient large current, it is required to connect a stabilizationcapacitor CDD with a large capacitance to an internal power supplyvoltage Vint (VDD) as described above and therefore, it is not easy tocontract a layout area for the NMOS down converter.

[0069] Besides, in a non-volatile memory, since a high voltage for writeand erase is used in the chip, there is a possibility to use not only aninternal power supply voltage Vint, which is decreased in an internalcircuit, but also part of an external power supply voltage Vext inperipheral circuits. For this reason, a further restriction on layoutarises in the NMOS down converter.

[0070] For example, since a high breakdown voltage transistor with athick gate oxide film is used for a charge pump circuit 14 shown in FIG.30, a power supply voltage of the charge pump circuit 14 is notnecessarily a decreased power supply voltage Vint. In addition, thecharge pump circuit 14 has large current consumption since the circuitcharges a comparatively large capacitance including a word line, a welland the like. When a decreased voltage Vint is used for a power supplyvoltage of the charge pump circuit 14, a power supply voltage Vint (VDD)of an internal circuit has a possibility to be unstable by receiving aninfluence of a large charge current since the current is suppliedthrough the voltage-decreasing NMOS (M10).

[0071] On the other hand, when an external power supply voltage Vext isused in the charge pump circuit 14, a circuit is required which switchesVext and Vint as a peripheral circuit to control the charge pump circuit14 and both of Vext and Vint are required to be supplied to a peripheralcircuit block. In such a manner, when a plurality of power supplycircuits coexists in the peripheral circuit block, there is a necessitythat an internal power supply voltage Vint which is supplied from a downconverter and an external power supply voltage Vext which is applied tothe down converter are both interconnected to the peripheral circuitblock, which makes overlap of power supply lines large.

[0072] In FIG. 33, there is shown an example of a layout of aconventional semiconductor integrated circuit: that is a memory,provided with a cell array 37; a down converter 38; a peripheral circuitblock 39 on a semi-conductor chip 36. Since it is a precondition that apower supply interconnection to the peripheral circuit block 39 isusually limited for Vint (VDD), if an external power supply voltage Vextis used in the peripheral circuit block 39, an interconnection for Vexthas required to be laid down in excess, thus producing an overhead of alayout area.

[0073] Further, in the conventional layout shown in FIG. 33, therearises a necessity for irregular power supply interconnection to leadout Vint (VDD) to the peripheral circuit block 39 from avoltage-decreasing NMOS included in the down converter 38. When theinterconnection is long, an unintentional parasitic resistance is addedto the source of the voltage-decreasing NMOS.

[0074] Since the down converter shown in FIG. 30 performs control sothat the source voltage of the voltage-decreasing NMOS (M10) isconstant, an exact control cannot be performed if a resistance is addedto the source. As described above, in a layout method for a conventionalNMOS down converter on a chip of a semiconductor integrated circuit,there has been a problem of increase in area due to extendedinterconnection and a problem of control of a power supply voltageaccompanying with the increase in area.

[0075] As described above, there has been a problem that in an internalpower supply of a conventional semiconductor integrated circuit, whenthe power supply voltage is temporarily decreased due to a powerconsumption of internal circuit, the power supply voltage detectingcircuit detects the decrease and resets latches erroneously.

[0076] Further, there has been another problem that in power supplycircuit of a down converter system provided with down converters, in astand-by mode and an active mode, when transition is effected from thestand-by mode with low power consumption to the active mode with highpower consumption, a temporary decrease in internal power supply voltageis hard to suppress.

BRIEF SUMMARY OF THE INVENTION

[0077] There has been many problems associated with designing and alayout area of NMOS and PMOS down converters employed in a conventionalsemiconductor integrated circuit of a multiple power supply type and ithas been difficult not only to meet requirements in miniaturization andrealization of higher integration for both down converters but to obtaina semiconductor integrated circuit of a multiple power supply type whichoperates according to the design using both down converters.

[0078] The present invention has been made in order to solve the abovedescribed problems and accordingly, it is an object of the presentinvention to provide a power supply voltage detecting circuit which willnot make a latch malfunction even if an internal power supply voltagechanges temporarily and provide down converters respectively in stand-byand active modes which suppress decrease in internal supply voltage intransition from the stand-by mode to the active mode, whose layoutrequire small areas, and which can be designed with ease.

[0079] A semiconductor integrated circuit of the present invention ischaracterized by that there is provided a power supply voltage detectingcircuit which avoids malfunction when a temporary change in power supplyvoltage occurs, by changing a detecting level according to increase ordecrease in power supply voltage.

[0080] A semiconductor integrated circuit of the present invention whichuses a PMOS down converter in a stand-by mode and an NMOS down converterin an active mode is characterized in that the decrease in internalpower supply voltage immediately after a transition from the stand-bymode to the active mode occurs is suppressed by setting the internalpower supply voltage in the stand-by mode higher than in the activemode.

[0081] A semiconductor integrated circuit of the present invention ischaracterized in that a down converter is formed in a lower layer of anexternal power supply interconnection. Peripheral circuit blocks towhich a decreased internal power supply voltage is supplied are formedin a lower layer of internal interconnection adjacent to both sides ofthe external power supply interconnection. Thereby, a distance betweenthe down converter and the peripheral circuit blocks to which theinternal supply voltage is supplied is minimized and further a decreasein voltage due to an interconnection resistance is avoided.

[0082] In a concrete manner of description, according to a first aspectof the present invention, there is provided a semiconductor integratedcircuit comprising a power supply voltage detecting circuit which, whena power supply voltage is higher than a first voltage, outputs a highlevel voltage, and when the power supply voltage is lower than the firstvoltage, outputs a low level voltage; and a detection signal outputcircuit which receives the output voltages of the power supply voltagedetecting circuit, and outputs a first detection signal when the powersupply voltage is increased to be equal to or higher than the firstvoltage, and a second detection signal when the power supply voltage isdecreased to a second voltage lower than the first voltage.

[0083] In the semiconductor integrated circuit according to the firstaspect of the present invention, the detection signal output circuit maycomprise a Schmitt trigger circuit.

[0084] According to a second aspect of the present invention, there isprovided a semiconductor integrated circuit comprising a first powersupply voltage detecting circuit which, when a power supply voltage ishigher than a first voltage, outputs a high level voltage, and when thepower supply voltage is lower than the first voltage, outputs a lowlevel voltage; and a second power supply voltage detecting circuitwhich, when the power supply voltage is higher than a second voltage,outputs a high level voltage, and when the power supply voltage is lowerthan the second voltage, outputs a low level voltage; and a detectionsignal output circuit which receives voltages of the output levels ofthe first and second power supply voltage detecting circuits, andoutputs a first detection signal when the power supply voltage isincreased to be equal to or higher than the first voltage, and a seconddetection signal when the power supply voltage is decreased to be equalto or lower than the second voltage which is higher than the firstvoltage.

[0085] In the semiconductor integrated circuit according to the secondaspect of the present invention, the detection signal output circuit maycomprise a flip-flop circuit to which the voltages of the output levelsof the first and second power supply voltage detecting circuits areinput.

[0086] According to a third aspect of the present invention, there isprovided a semiconductor integrated circuit in which an external powersupply voltage supplied externally is decreased and an internal powersupply voltage for driving an internal circuit is generated, comprisingan external power supply voltage detecting circuit which detects theexternal power supply voltage; and an internal power supply voltagedetecting circuit which detects the internal power supply voltage,wherein the internal power supply voltage detecting circuit is comprisedof a power supply voltage detecting circuit which, when the internalpower supply voltage is increased to be equal to or higher than a firstvoltage, outputs a first detection signal, and when the power supplyvoltage is decreased to be equal to or lower than a second voltage whichis lower than the first voltage, outputs a second detection signal.

[0087] According to a fourth aspect of the present invention, there isprovided a semiconductor integrated circuit in which an external powersupply voltage supplied externally is decreased and an internal powersupply voltage for driving an internal circuit is generated, comprisingan external power supply voltage detecting circuit which detects theexternal power supply voltage; and an internal power supply voltagedetecting circuit which detects the internal power supply voltage,wherein the external power supply voltage detecting circuit and theinternal power supply voltage detecting circuit have respective powersupply voltage detection levels different from each other.

[0088] According to a fifth aspect of the present invention, there isprovided a semiconductor integrated circuit in which an external powersupply voltage supplied externally is decreased and an internal powersupply voltage for driving an internal circuit is generated, wherein theinternal power supply voltage is set to a first voltage in a stand-bymode of the semiconductor integrated circuit and a second voltage in anactive mode of the semiconductor integrated circuit, and wherein thefirst voltage in the stand-by mode is set higher than the second voltagein the active mode.

[0089] According to a sixth aspect of the present invention, there isprovided a semiconductor integrated circuit in which an external powersupply voltage supplied externally is generated and an internal powersupply voltage for driving an internal circuit is generated, comprisinga stand-by mode down converter; a voltage switching circuit for thestand-by mode down converter; an active mode down converter; an enablesignal generating section which makes the active mode down converter tobe an enable state; and a stabilization capacitor which stabilizes theinternal power supply voltage, wherein an output terminal of the enablesignal generating section is connected to the active mode down converterand the voltage switching circuit in parallel, and wherein an internalpower supply voltage in an stand-by mode is set higher than an internalpower supply voltage in an active mode.

[0090] In the semiconductor integrated circuit according to the sixthaspect of the present invention, when a time period from when an enablesignal is output from the enable signal generating section till theactive mode down converter reaches an operating state is denoted byTact, an average current of the internal circuit during the time periodTact by lint, a capacitance of a stabilization capacitor by C, aninternal power supply voltage in a stand-by mode by Vstby and aninternal power supply voltage in an active mode by Vint, a relation ofC×(Vstby−Vint)/Tact>Iint may be established.

[0091] According to a seventh aspect of the present invention, there isprovided a semiconductor integrated circuit in which an external powersupply voltage supplied externally is decreased and an internal powersupply voltage for driving an internal circuit is generated, comprisinga stand-by mode down converter; and an active mode down converter whichconstitutes together with the stand-by mode down converter a downconverter for the external power supply voltage, wherein the stand-bymode down converter includes a comparator of a differentialamplification type to one of whose input terminals a reference voltageis input; a P channel transistor, whose source is connected to anexternal power supply line which supplies the external power supplyvoltage, whose gate is connected to an output terminal of thecomparator, and whose drain is connected to an internal power supplyline which supplies the internal power supply voltage; and a resistancevoltage divider which divides a voltage of the drain over resistancevalues of resistors and inputs a divided voltage to the other of theinput terminals of the comparator, and wherein the active mode downconverter includes a voltage generating circuit; and an N channeltransistor, whose drain is connected to the external power supply linewhich supplies the external power supply voltage, whose gate isconnected to an output terminal of the voltage generating circuit, andwhose source is connected to the internal power supply line whichsupplies the internal power supply voltage.

[0092] In the semiconductor integrated circuit according to the seventhaspect of the present invention, the voltage generating circuit mayinclude a charge pump circuit and a voltage limiter. In thesemiconductor integrated circuit, the voltage generating circuit mayinclude a resistor which is connected between an output terminal of thecharge pump circuit and an input terminal of the voltage limiter.

[0093] In the semiconductor integrated circuit according to the seventhaspect of the present invention, the voltage generating circuit mayinclude a comparator of a differential amplification type to one ofwhose input terminals a reference voltage is input; a P channeltransistor, whose source is connected to the external power supply linewhich supplies the external power supply voltage, whose gate isconnected to an output terminal of the comparator, and whose drain is anoutput terminal; and a resistance voltage divider which divides avoltage of the drain over resistance values of resistors and inputs adivided voltage to the other of the input terminals of the comparator.

[0094] In the semiconductor integrated circuit according to the seventhaspect of the present invention, the semiconductor integrated circuitmay further comprise a rectifying element inserted between the outputterminal of the voltage generating circuit and the external power supplyline which supplies the external power supply voltage, the rectifyingelement for allowing a current to flow in a direction from a terminal ofthe external power supply voltage to the output terminal of the voltagegenerating circuit.

[0095] In the semiconductor integrated circuit according to the seventhaspect of the present invention, the semiconductor integrated circuitmay further comprise a stabilization capacitor for an output voltageconnected to the output terminal of the voltage generating circuit, acapacitance of the stabilization capacitor being smaller than a gatecapacitance of the N channel transistor.

[0096] In the semiconductor integrated circuit according to the seventhaspect of the present invention, the semiconductor integrated circuitmay further comprise a P channel transistor, a source of the P channeltransistor being connected to the external power supply line whichsupplies the external power supply voltage and a drain thereof beingconnected to the internal power supply line which supplies the internalpower supply voltage, and a charging accelerating circuit foraccelerating charging of the internal power supply line by holding the Pchannel transistor in an ON state during a time period from when anexternal power supply voltage is applied till an internal power supplyvoltage reaches a prescribed voltage lower than a target value.

[0097] According to an eighth aspect of the present invention, there isprovided a semiconductor integrated circuit comprising a down converterwhich generates an internal power supply voltage on a semiconductor chipfrom an external power supply voltage which is supplied from the outsideof the semiconductor chip; and a charge pump circuit which generates aboosted voltage on the semiconductor chip from the external power supplyvoltage.

[0098] According to a ninth aspect of the present invention, there isprovided a semiconductor integrated circuit comprising a down converterwhich generates an internal power supply voltage on a semiconductor chipfrom an external power supply voltage which is supplied from the outsideof the semiconductor chip; and an external power supply line whichsupplies the external power supply voltage and an internal power supplyline which supplies the internal power supply voltage, wherein theexternal power supply line and the internal power supply line arearranged in parallel to each other on the semiconductor chip, andwherein the down converter is arranged in a lower layer of the externalpower supply line, whereby the internal power supply voltage which isgenerated in the down converter is supplied to a peripheral circuitblock adjacent to the down converter.

[0099] According to a tenth aspect of the present invention, there isprovided a semiconductor integrated circuit comprising a down converterwhich generates an internal power supply voltage on a semiconductor chipfrom an external power supply voltage supplied from the outside of thesemiconductor chip; and an external power supply line which supplies theexternal power supply voltage and an internal power supply line whichsupplies the internal power supply voltage, the external power supplyline and the internal power supply line being arranged on thesemiconductor chip, wherein the down converter is arranged in a lowerlayer of the external power supply line, and wherein a connection leadsection of the external power supply line and the internal power supplyline are arranged in a superposing manner, whereby the external powersupply voltage and the internal power supply voltage are supplied to aperipheral circuit block adjacent to the down converter.

[0100] According to an eleventh aspect of the present invention, thereis provided a semiconductor integrated circuit comprising a downconverter on a semiconductor chip, which generates an internal powersupply voltage from an external power supply voltage supplied from theoutside of the semiconductor chip; an external power supply line whichsupplies the external power supply voltage, the external power supplyline and the down converter which is formed in a lower layer of theexternal power supply line being both formed in a region of thesemiconductor chip, which region extends in a direction; a peripheralcircuit to which the internal power supply voltage is supplied from thedown converter constructed of at least two peripheral circuit blockswhich are symmetrically arranged on both sides of the region extendingin the direction, and an internal power supply line which supplies theexternal power supply voltage, wherein the internal power supply lineand the at least two peripheral circuit blocks to which blocks theinternal power supply voltage is supplied are arranged so as to beadjacent to the region extending in the direction, and wherein theinternal power supply voltage is supplied to the at least two peripheralcircuit blocks by way of the internal power supply line.

[0101] According to a twelfth aspect of the present invention, there isprovided a semiconductor integrated circuit comprising a first powersupply voltage detecting circuit which, when a power supply voltage ishigher than a first voltage, outputs a high level voltage, and when thepower supply voltage is lower than the first voltage, outputs a lowlevel voltage; and a second power supply voltage detecting circuit whichwhen the power supply voltage is higher than a second voltage, outputs ahigh level voltage, and when the power supply voltage is lower than thesecond voltage, outputs a low level voltage; and a detection signaloutput circuit which receives voltages of the output levels of the firstand second power supply voltage detecting circuits, and outputs a firstdetection signal when the power supply voltage is increased to be equalto or higher than the first voltage, and a second detection signal whenthe power supply voltage is decreased to be equal to or lower than thesecond voltage which is lower than the first voltage.

[0102] In the semiconductor integrated circuit according to the twelfthaspect of the present invention, the detection signal output circuit maycomprise a flip-flop circuit to which the voltages of the output levelsof the first and second power supply voltage detecting circuits areinput.

[0103] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0104] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0105]FIG. 1 is a diagram showing a configuration of a power supplyvoltage detecting circuit of a first embodiment of the presentinvention.

[0106]FIGS. 2A and 2B are an illustration and a graph showing ahysteresis characteristic of a Schmitt trigger circuit.

[0107]FIG. 3 is a diagram showing a configuration of a power supplyvoltage detecting circuit of a second embodiment of the presentinvention.

[0108]FIG. 4 is a timing chart showing operations of a power supplyvoltage detecting circuit of the second embodiment of the presentinvention.

[0109]FIG. 5 is a diagram showing a configuration of a power supplyvoltage detecting circuit of a third embodiment of the presentinvention.

[0110]FIG. 6 is a timing chart showing operations of a power supplyvoltage detecting circuit of the third embodiment of the presentinvention.

[0111]FIG. 7 is a diagram showing a configuration of a power supplyvoltage detecting circuit of a fourth embodiment of the presentinvention.

[0112]FIG. 8 is a timing chart showing operations of a power supplyvoltage detecting circuit of the fourth embodiment of the presentinvention.

[0113]FIG. 9 is a diagram showing details of a Schmitt trigger circuitused in a fifth embodiment of the present invention.

[0114]FIG. 10 is a block diagram showing a configuration of a downconverter of a sixth embodiment of the present invention.

[0115]FIG. 11 is a diagram showing a configuration of a modification ofthe down converter of the sixth embodiment of the present invention.

[0116]FIG. 12 is a diagram showing details of the configuration of adown converter of the sixth embodiment of the present invention.

[0117]FIG. 13 is a diagram showing a circuit configuration of a PMOSstand-by mode down converter of a seventh embodiment of the presentinvention.

[0118]FIG. 14 is a diagram showing a circuit configuration of an NMOSactive mode down converter of an eighth embodiment of the presentinvention.

[0119]FIG. 15 is a diagram showing a configuration of a charge pumpcircuit.

[0120]FIG. 16 is a diagram showing a configuration of a level shifter.

[0121]FIGS. 17A and 17B are diagrams showing configurations of a voltagelimiter.

[0122]FIG. 18 is a diagram showing a configuration of a referencevoltage generating circuit.

[0123]FIG. 19 is a diagram showing a modification example of an NMOSactive mode down converter.

[0124]FIG. 20 is a diagram showing means for high-speed increase ininternal power supply voltage.

[0125]FIG. 21 is a graph of a characteristic illustrating the means forhigh-speed increase in internal power supply voltage.

[0126]FIG. 22 is a diagram showing a modification example of a PMOSstand-by mode down converter.

[0127]FIG. 23 is an illustration showing a layout of power supplyinterconnection of a ninth embodiment of the present invention.

[0128]FIG. 24 is an illustration showing a layout of a down converterand power supply interconnection of the ninth embodiment of the presentinvention.

[0129]FIG. 25 is a conceptual illustration showing a layout of asemiconductor integrated circuit of the ninth embodiment of the presentinvention.

[0130]FIG. 26 is a sectional view illustrating an erase operation of aNAND EEPROM and a problematic point thereof.

[0131]FIG. 27 is a diagram showing a configuration of a conventionalpower supply voltage detecting circuit.

[0132]FIG. 28 is a block diagram showing a configuration of aconventional down converter.

[0133]FIG. 29 is a diagram showing a configuration of a conventionalPMOS down converter.

[0134]FIG. 30 is a diagram showing a configuration of a conventionalNMOS down converter.

[0135]FIGS. 31A and 31B are a diagram and a graph showing asub-threshold characteristic of a voltage decreasing NMOS.

[0136]FIG. 32 is a block diagram showing a configuration of conventionalstand-by/active mode down converter.

[0137]FIG. 33 is a conceptual plan view showing a layout of aconventional semiconductor integrated circuit.

DETAILED DESCRIPTION OF THE INVENTION

[0138] Embodiments of the present invention will below be detailed withreference to the accompanying drawings. FIG. 1 is a diagram showing aconfiguration of a power supply voltage detecting circuit of a firstembodiment of the present invention. A power supply voltage detectingcircuit of the first embodiment is provided with different voltagedetection levels respectively in increase and decrease in voltage sothat, when a power supply voltage level is temporarily decreased, thepower supply voltage detecting circuit does not reset a latch even ifthe circuit detects the temporary decrease in the power supply voltage.

[0139] Such a power supply voltage detecting circuit as meets the abovedescribed performance can be realized in several methods. The easiestand most simple method among them is shown in FIG. 1. The power supplyvoltage detecting circuit of FIG. 1 comprises: a power supply voltagedetecting section 1 including serially connected resistors R1 and R2 oneof whose terminals is connected to a power supply and the other of whoseterminals is connected to the drain of NMOS (M1) connected as a diode;PMOS (M2) whose source is connected to the power supply and whose drainis an output end; a resistor R3 which is connected to between the drainand ground; and a stabilization capacitor C1 which is connected tobetween the drain and ground in parallel to the resistor R3; and aSchmitt trigger circuit 2.

[0140] Incidentally, in the power supply voltage detecting circuit ofFIG. 1, the source of NMOS (M1) is grounded and there are provided anode N1 which connects an intermediate terminal of the seriallyconnected resistors R1 and R2 and the gate of PMOS (M2) with each otherand a node N2 which connects the drain of PMOS (M2) and the inputterminal of the Schmitt trigger circuit 2 with each other. A power-onsignal Vpwon is output from the output terminal of the Schmitt triggercircuit 2.

[0141] Since a circuit configuration of the power supply voltagedetecting section 1 of FIG. 1 is same as that of the power supplyvoltage detecting circuit of FIG. 27 except for a stabilizationcapacitor C1, and inverters 15 and 16, detailed description of a circuitoperation of the power supply voltage detecting section is omitted.Input/output terminals IN and OUT of the Schmitt trigger circuit areshown in FIG. 2A and an input/output characteristic of the Schmitttrigger circuit are shown in FIG. 2B.

[0142] As described above, the node N2 goes “H” or “L” according towhether a power supply voltage V is higher or lower than Vpwon. While,when the power supply voltage V is increased, a power-on signal isgenerated at the level of Vpwon (Vb of FIG. 2B) since a voltage of thenode N2 is input to the Schmitt trigger circuit which has aninput/output characteristic in the form of a hysteresis as shown in FIG.2B, when the power supply voltage V is decreased, a signal is notgenerated even if the power supply V is decreased to Vpwon since adetection level of the Schmitt trigger circuit is lowered (Va of FIG.2B).

[0143] When the power supply voltage is decreased, if the power supplyvoltage V is decreased to a value lower than Vpwon, thereby, PMOS (M2)becomes the OFF state and in succession, a voltage of the node N2 isvery rapidly decreased to Va, the Schmitt trigger circuit 2 generates adetection signal, which makes a change in detection level meaningless.In order to avoid this, a capacitor C1 with a sufficiently largecapacitance is connected to the node N2. With the capacitor C1, avoltage of the node N2 is maintained due to a delay time of C1×R3 andthe power supply voltage is decreased before the voltage of the node N2is decreased, so that the Schmitt trigger circuit 2 never generates adetection signal.

[0144] Then, a power supply voltage detecting circuit according to asecond embodiment of the present invention will be described based onFIGS. 3 and 4. In the first embodiment, description is made on a powersupply voltage detecting circuit which is designed so as not to generatea signal in a substantial sense when the power supply voltage isdecreased, but in the second embodiment shown in FIG. 3, descriptionwill be made on a power supply detecting circuit in which signals aregenerated both in increase and decrease in the power supply voltage anda detection level in the increase is set to higher than that in thedecrease.

[0145] The power supply voltage detecting circuit shown in FIG. 3 has asimilar configuration of the power supply voltage detecting circuit inFIG. 1 and comprises: a first power supply voltage detecting section 1including NMOS (M1), PMOS (M2), resistors R1, R2 and R3 and nodes N1 andN2; a second power supply voltage detecting section 3 including NMOS(M1′), PMOS (M2′), resistors R1′, R2′ and R3′ and nodes N1′ and N2′; anincrease signal detecting circuit 4 including a NAND gate G1, a delay(delay circuit) D1, and inverters 13 and 14; a decrease signal detectingcircuit 5 including a NAND gate G2, a delay (delay circuit) D2, and aninverter 17; and a flip-flop 6 including NOR gates G3 and G4.

[0146] Incidentally, the first power supply voltage detecting section 1and the decrease signal detecting circuit 5 are connected to each otherthrough the inverters 15 and 16 and the decrease signal detectingcircuit 5 is provided with a node N3 which is an output section.Further, the second power supply voltage detecting section 3 and theincrease signal detecting circuit 4 are connected to each other throughinverters I1 and I2 and the increase signal detecting circuit 4 isprovided with a node N3′ which is an output section.

[0147] As described above, the first power supply voltage detectingsection 1 shown in FIG. 3 is a circuit a potential of whose node N2 goes“H” if the power supply voltage is higher than V1 which is given by

V1=Vtn+(R1+R2)×|Vtp|/R1  (4)

[0148] , where Vtn and Vtp are respectively threshold voltages of NMOS(M1) and PMOS (M2).

[0149] Like this, the second power supply voltage detecting section 3 isa circuit a potential of whose N2′ goes “H” if the power supply voltageis higher than V2 which is given by

V2=Vtn+(R1′+R2′)×|Vtp|/R2′  (5)

[0150] Values of resistance of the resistors R1, R2 and R1′, R2′ are setso as to be V2>V1.

[0151] Operations of a power supply voltage detecting circuit shown inFIG. 3 will be described using a timing chart of FIG. 4.

[0152] Time dependence of the power supply voltage V is shown in theuppermost chart of FIG. 4. In an increase region of the power supplyvoltage V, if V goes higher than V1, a voltage VN2 of the node N2 in thefirst power supply voltage detecting section 1 goes “H” as shown in thesecond highest chart. If V goes higher than V2, a voltage VN2′ of thenode N2′ of the second power supply voltage detecting circuit 3 goes “H”as shown in the third highest chart.

[0153] VN2 is transferred to the decrease signal detecting circuit 5through the inverters I5 and I6 and input to one of the input terminalsof a NAND gate G2. Further VN2 is branched away to an inverter I7 anddelay D2 and input to the other input terminal of the NAND gate G2.Accordingly, one of the two inputs of the NAND gate G2 goes “H” and, asshown in the fourth highest chart, no increase in VN2 is detected and a“L” state is maintained in a voltage VN3 of the node N3 in the outputsection of the decrease signal detecting circuit 5.

[0154] On the other hand, VN2′ is transferred to the increase signaldetecting circuit 4 through the inverters I1 and I2 and input to one ofthe input terminals of a NAND gate G1. Further VN2′ is branched away toan inverter 13 and delay D1 and input to the other of the input terminalof the NAND gate G1. Accordingly, the two inputs of the NAND gate G1 arekept “H” during a delay time of the delay D1 only and, as shown in thefifth highest chart, a voltage VN3′ of the node N3′ in the outputsection of the increase signal detecting circuit 4 generates an increasesignal detection pulse with a pulse width equal to the delay time at apoint in time when V=V2.

[0155] Then, if V is lower than V2 in the decrease region of the powersupply voltage V, a voltage VN2′ of the node N2′ of the second powersupply voltage detecting section 3 inverts from “H” to “L” as shown inthe third highest chart. If V is lower than V1, a voltage VN2 of thenode N2 in the first power supply voltage detecting section 1 invertsfrom “H” to “L” as shown in the second highest chart.

[0156] VN2″ is transferred to the increase signal detecting circuit 4through the inverters I1 and I2 and input to one of the terminals of theNAND gate G1. Further, VN2′ is branched away to the inverter 13 and thedelay D1 and input to the other of the input terminals of the NAND gateG1. Accordingly, one of the two inputs of the NAND gate G2 goes “H” orboth of the two inputs go “L” and, as shown in the fifth highest chart,no decrease in VN2′ is detected and a “L” state is maintained in avoltage VN3′ of the node N3′ in the output section of the increasesignal detecting circuit 4.

[0157] On the other hand, VN2 is transferred to the decrease signaldetecting circuit 5 through the inverters I5 and I6 and input to one ofthe input terminals of the NAND gate G2. Further, VN2 branches away tothe inverter 17 and the delay D2 and input to the other of the inputterminals of the NAND gate G2. Accordingly the two input of the NANDgate G2 is kept at “L” during the delay time of the delay D2 only and,as shown in the fourth highest chart, a voltage VN3 of the node N3 inthe output section of the decrease signal detecting circuit 5 generatesa decrease signal detection pulse with a pulse width equal to the delaytime at a point in time when V=V1.

[0158] In such a manner, when the power supply voltage V is increased tobe higher than V2 and when the power supply voltage V is decreased to belower than V1, increase and decrease signal detection pulses arerespectively generated by the increase signal detecting circuit 4 andthe decrease signal detecting circuit 5.

[0159] If the pulses are input to the flip-flop 6, the power supplyvoltage detecting circuit of FIG. 3 outputs a power-on signal Vpwonwhich keeps “H” during the time from when the power supply voltage Vexceeds V2 till being decreased to be lower than V1, as shown in thelowest chart of FIG. 4.

[0160] A power supply voltage detecting circuit of the second embodimenthas an advantageous point that detection levels in the increase anddecrease are freely changed as far as V2>V1 by changing resistancevalues of the resistors R1, R2, R1′ and R2′ as seen from the equations(4) and (5), and an inequality shown in the top right side of FIG. 3.

[0161] Then, a power supply voltage detecting circuit according to athird embodiment of the present invention will be described based onFIGS. 5 and 6. The third embodiment is a modification example of thesecond embodiment and a power supply voltage detecting circuit in whichsignals are generated both in the increase and decrease in the powersupply voltage and in addition, a detection level in the increase is sethigher than that in the decrease like the second embodiment in term offunctionality.

[0162] As shown in FIG. 5, the power supply voltage detecting circuit ofthe third embodiment is different from the second embodiment in that theincrease signal detecting circuit 4 and the decrease signal detectingcircuit 5 are both removed compared with the second embodiment and aninverter 18 is added in an output section of a power supply voltagedetecting section 1. Accordingly, VN2′ and /VN2 which is obtained byinverting VN2′ with the inverter 18 are input to input terminals of theflip-flop 6.

[0163]FIG. 6 is a timing chart showing operations of the power supplyvoltage detecting circuit of the third embodiment. If the circuitconfiguration of FIG. 5 is employed, a power-on signal Vpwon which isabsolutely same as that of FIG. 4 can be output in the increase anddecrease in the power supply voltage.

[0164] Further, there is available an advantage that detection levels inthe increase and decrease can freely be changed as far as V2>V1 bychanging resistance values of the resistors R1, R2, R1′ and R2′ as shownin the inequality in the top right side of FIG. 5. Incidentally, sinceoperations of constituents are similar to those of the secondembodiment, descriptions thereof are omitted.

[0165] The power supply voltage detecting circuit of the thirdembodiment is simple in circuit configuration compared with the secondembodiment since the increase and decrease signal detecting circuitsdescribed in the second embodiment are omitted, whereas the secondembodiment is superior to the third embodiment in terms of sureness ofoperations.

[0166] Then, a power supply voltage detecting circuit according to afourth embodiment of the present invention will be described based onFIGS. 7 and 8. The fourth embodiment is a modification example of thesecond embodiment and a power supply voltage detecting circuit in whichsignals is generated both in increase and decrease in the power supplyvoltage and a detection level in the decrease is set higher than that inthe increase, which is different from the second embodiment.

[0167] The fourth embodiment is different from the second embodimentcompared therewith in that a first power supply voltage detectingcircuit 1 in which if the power supply voltage goes higher than V1, apotential of the node N2 goes “H” and an increase signal detectingcircuit 4 are connected with each other through two inverters I5 and I6;and further, a second power supply voltage detecting section 3 in whichif the power supply voltage is higher than V2 (V2>V1), a potential of anode N2′ goes “H” and a decrease signal detecting circuit 5 is connectedwith each other through two inverters cascaded I1 an I2.

[0168]FIG. 8 is a timing chart showing operations of a power supplyvoltage detecting circuit in the fourth embodiment. Since a first powersupply voltage detecting section 1 whose detection level (V1) is low isconnected to an increase signal detecting circuit 4, an increase signaldetection pulse is generated at a point in time when V=V1 in VN3 of thefourth highest chart VN3, while since a second power supply voltagedetecting circuit 3 whose detection level (V2) is high is connected to adecrease signal detecting circuit 5, a decrease signal detection pulseis generated in VN3′ of the fifth highest chart at a point in time whenV=V2 (V2>V1).

[0169] Accordingly, as shown in the lowest chart of FIG. 8, a power-onsignal Vpwon outputs “H” level during the time when the power supplyvoltage exceeds V1 till the power supply voltage is deceased to be lowerthan V2. Further, there is available an advantage that as shown in aninequality in the top right side of FIG. 7, detection levels in theincrease and decrease can be freely selected as far as V2>V1 by changingresistance values of the resistors R1, R2, R1′ and R2′. Incidentally,since operations of constituents are similar to those in the secondembodiment, descriptions thereof are omitted.

[0170] In such a manner, contrary to the second and third embodiments, apower-on circuit in which a detection level in the increase is lowerthan that in the decrease can be configured. Such a power supply voltagedetecting circuit is effective for the following case for example.

[0171] Even if a detection level of the power supply voltage detectingcircuit is set low to some extent in increase in the power supplyvoltage, the circuit has a low possibility to malfunction since thepower supply voltage is further increased at a point in time when adetection signal reaches a circuit on the receiver side.

[0172] However, when the power supply voltage is rapidly decreased,there can arise a situation in which a logic circuit does not operatesince the power supply voltage is further decreased at a point in timewhen a detection signal reaches a circuit on the receiver side.

[0173] As described above, when it is required to perform a prescribedrecovery operation, by detecting a decrease in the power supply voltage,a trouble that a logic circuit does not operate can occur. On thisoccasion, if the power supply voltage detecting circuit of the fourthembodiment is used and detection can be performed in an advanced timingin the decrease in the power supply voltage, a recovery operation whenthe power supply voltage is decreased can surely be performed.

[0174] In the first to fourth embodiments, while descriptions are madeof the power supply voltage detecting systems in which a power-on signalis output in increase and decrease in power supply voltage, acombination of the embodiments or a combination of the embodiments withconventional examples will make it possible that a semiconductorintegrated circuit of a multiple power supply type is provided withdifferent supply voltage detecting circuits corresponding to respectivepower supply voltages.

[0175] As for a semiconductor integrated circuit using a down converter,while, conventionally, the same detection level has been applied to anexternal power supply voltage Vext and an internal power supply voltageVint, the same detection level has been applied in increase and decreasein the power supply voltage as well and still further, power supplyvoltage detecting circuits with the same configuration as each otherhave been used in all cases, according to the present invention, suchcombinations in a conventional case can be changed to the followingcombinations:

[0176] (1) A power supply voltage detection circuit in the fourthembodiment is employed for an external power supply voltage Vext and apower supply voltage detection circuit of the second embodiment isemployed for an internal supply voltage Vint. With such a configuration,decrease in external power supply voltage can be detected in an advancedtiming.

[0177] (2) A conventional power supply voltage detecting circuit inwhich the same detection level is applied for increase and decrease inpower supply voltage is employed for an external power supply voltageVext and a power supply voltage detection circuit of the secondembodiment is employed for an internal power supply voltage Vint. Withsuch a configuration, when the power supply voltage is temporarilydecreased, a power-on signal is generated and therefore, a problem thata latch is reset can be avoided.

[0178] (3) Conventional power supply voltage detecting circuits in eachof which the same detection level is applied for increase and decreasein power supply voltage are both employed for an external power supplyvoltage Vext and an internal power supply voltage Vint, but detectionlevels of the respective circuits for Vext and Vint are differently settherebetween. With such a configuration and an operating condition, adetection sensitivity to a change in internal power supply voltage Vintcan be increased.

[0179] If several kinds of the power supply voltage detecting circuitsin combination are employed in such a manner, a power-on sequence withflexibility can be realized, in which characteristics of power suppliesare reflected.

[0180] Then, a power supply voltage detecting circuit of a fifthembodiment of the present invention will be described based on FIG. 9.In a semiconductor integrated circuit in which an external power supplyvoltage Vext is used and an internal power supply voltage Vint is usedwhich is generated by decreasing Vext in a down converter and applied toan internal circuit, a power supply voltage detection circuit of thefifth embodiment is at least constituted of a Vint power supply voltagedetecting circuit, wherein a first detection signal is output when Vintis increased to be equal to or higher than a first voltage prescribedand a second detection signal is output when Vint is decreased to beequal to or lower than a second voltage which is lower than the firstvoltage.

[0181] A power supply voltage detecting circuit for Vint with such acharacteristic can be obtained by adopting power supply voltagedetecting circuits of the first and second embodiments for Vint. Thatis, in the power supply voltage detecting circuits of the first andsecond embodiments which are shown in FIGS. 1 and 3, Vint is onlyrequired to be handled as a power supply voltage.

[0182] Since an external power supply voltage Vext and an internal powersupply voltage Vint are required to be differentiated from each other indiagrams in which the following embodiments relating to a semiconductorintegrated circuit of a multiple power supply type are respective shown,a power supply terminal for Vext is marked by a black circle and a powersupply terminal for Vint is marked by a circle. While power supplyterminals are marked by black circles in FIGS. 1, 3, 5 and 7 used fordescription of the first to fourth embodiments, the black circles arenot necessarily limited to Vext, but when the embodiments are applied toan internal power supply, the black circles may be changed to circleswhich indicate Vint.

[0183] In the fifth embodiment, description will be made, as an example,on a case where a power supply voltage detecting circuit which issimilar to the first embodiment in which a power supply voltagedetecting section and a Schmitt trigger circuit are connected with eachother is employed especially as a power supply voltage detecting circuitfor Vint.

[0184] In FIG. 9, details of a configuration of a Schmitt triggercircuit employed in the fifth embodiment will be shown. A power supplyvoltage detecting circuit for Vint of the fifth embodiment comprises: aSchmitt trigger circuit constructed of CMOS inverters shown in FIG. 9and the power supply voltage detecting section 1 shown in FIG. 1 both ofwhich are connected with each other. In this case, an internal powersupply voltage Vint which is generated by decreasing an external powersupply voltage Vext in a down converter on a chip is connected to powersupply terminals of both circuits.

[0185] The Schmitt trigger circuit shown in FIG. 9 comprises: a CMOSinverter 19 constructed of NMOS (M3) and PMOS (M4); a CMOS inverter I10constructed of NMOS (M5) and PMOS (M6); and a feed-back circuit, whichis constructed of NMOS (M7 and M8), and in which an output of I10 is fedback to an input terminal of I10 by supplying an output voltage of I10to the gates of NMOS (M7 and M8). Incidentally, C2 is a capacitor whichreinforces the function of C1 of FIG. 1 which is described above, N2corresponds to the node N2 in the output section of the power supplyvoltage detecting section shown in FIG. 1 and N3 and N4 respectivelyindicate the nodes in the interior and output section of the Schmitttrigger circuit.

[0186] As described above using the equations (1) and (2), when aninternal power supply voltage Vint is increased to be higher than Vpwon,the node N2 changes from “L” to “H.” That is, since an input IN of theSchmitt trigger circuit shown in FIG. 9 changes from “L” to “H,” anoutput N3 of the CMOS inverter I9 at the first stage changes from “H” to“L.” Accordingly, an output N4 of the CMOS inverter I10 at the nextstage becomes the “H” state and a power-on signal is generated.

[0187] The “H” state of N4 is fed back to the gates of NMOS M7 and M8,and NMOS M7 and M8 is set in the ON state and therefore, the N3 isgrounded to go “L” and that is, the output OUT of the Schmitt triggercircuit is retained at “H.”

[0188] Then, when Vint is decreased to be lower than Vpwon, the node N2changes from “H” to “L.” Accordingly, while NMOS (M3) is off and PMOS(M4) is on in the first stage inverter, so that N3 is connected to Vintthrough PMOS (M4), on the other hand since N3 is grounded by NMOS (M7and M8), the “L” state of N3 is retained and therefore, a power-onsignal is not generated at Vpwon when Vint is deceased. Further, if Vintis sufficiently decreased and a retaining function of the feed-backcircuit constructed of NMOS (M7 and M8) is reduced, N3 is restored to“H” and accordingly, the output OUT of the Schmitt trigger circuit isrestored to “L.”Incidentally, while the input/output characteristics ofthe Schmitt trigger circuit which is described herein inverts a logic ofFIG. 2B, the characteristics are not problematic in practical use sincethe circuit has a hysteresis characteristic.

[0189] In the mean time, in the power supply voltage detecting circuitof the fifth embodiment, while detection levels can be changed accordingto when an internal power supply voltage is increased or decreased byusing the hysteresis characteristic of a Schmitt trigger circuit, forexample, when a 2-input AND gate is connected to the output section ofthe power supply voltage detecting circuit and AND of the output of thepower supply voltage detecting section of FIG. 1 and the output of thepower supply voltage detecting circuit of FIG. 5 is taken, it ispossible that a power-on signal is not generated in an absolute sensewhen the internal power supply voltage Vint is decreased since bothoutputs do not coincide with each other during the decrease in theinternal power supply voltage Vint.

[0190] The reason why a power-on signal is not output when Vint isdecreased in such a manner is that, for example, when a semiconductormemory is in a sense operation, since an internal voltage Vint(corresponds to VDD voltage of an internal circuit) can be temporarilydecreased down to equal to or lower than 2V, a measure is adopted sothat a power-on signal is prevented from being generated in anunprepared manner.

[0191] Then, a down converter according to a sixth embodiment of thepresent invention will be described based on FIGS. 10 and 11. The sixthembodiment is a semiconductor integrated circuit of a multiple powersupply type which is provided with down converters for stand-by andactive modes in which the down converters suppress a temporary decreasein internal power supply voltage Vint immediately after transition fromthe stand-by mode to the active mode. In order to avoid the temporarydecrease in internal power supply voltage from occurring, it is onlyrequired to set an internal power supply voltage Vstby in the stand-bymode higher than the internal power supply voltage Vint in the activemode.

[0192]FIG. 10 is a block diagram showing a configuration of such downconverter. The down converter of FIG. 10 comprises: an enable signalgenerating section 7 for an active mode down converter; a voltageswitching circuit 8; a stand-by mode down converter 9; the active modedown converter 10; an internal circuit 11; and a stabilization capacitorC3 connected to a power supply line of the internal circuit 11.

[0193] An external power supply voltage Vext is supplied to the stand-bymode down converter 9 and the active mode down converter 10, an internalpower supply voltage Vint which is obtained by decreasing of Vext at aprescribed ratio is supplied to the internal circuit 11 in the activemode of the semiconductor integrated circuit, while an internal powersupply voltage Vstby which is obtained by decreasing of Vext at anotherratio is supplied to the internal circuit in the stand-by mode thereof,wherein an inequality Vstby>Vint is maintained. Incidentally, in FIG.10, there is shown a state in which Vint is applied to the internalcircuit 11 in the active mode. In the stand-by mode, Vint is switched toVstby.

[0194] That is, an enable signal output from the enable signalgenerating section 7 for the active mode down converter is input to thevoltage switching circuit 8 of the stand-by down converter 9 and theactive mode down converter 10 in parallel. The stand-by down converter 9receives an output of the voltage switching circuit 8 and sets theinternal power supply voltage Vstby for the stand-by mode when thesemiconductor integrated circuit is in the stand-by mode, while settingthe internal power supply voltage Vint for the active mode when thesemiconductor integrated circuit is in the active mode.

[0195] Further, it is allowed that a delay circuit D3 is inserted in aninput section of the voltage switching circuit 8 as shown in FIG. 11 andthe stand-by mode down converter 9 continues to retain the power supplyvoltage Vstby in the stand-by mode till the active mode down converter10 reaches the operating state.

[0196] Then, the reason why, if a stabilization capacitor C3 isconnected to a power supply line of the internal circuit as describedabove and the power supply voltage Vstby in the stand-by mode is sethigher than the power supply voltage Vint in the active mode, atemporary decrease in the internal power supply voltage Vint in thetransition from the stand-by mode to the active mode can be avoided willbe described.

[0197] When a capacitance of the stabilization capacitor C3 is denotedby C, a rise time of the active mode down converter by Tact, and anaverage current supplied onto the power supply line of the internalcircuit from C3 till the active mode down converter reaches an operatingstate by Iav, the average current expressed by the following equation(6) is supplied onto the power supply line of the internal circuitduring the time in which the active mode down converter reaches anoperating state:

Iav=C×(Vstby−Vint)/Tact  (6)

[0198] If Vstby is set so that a value of the Iav grows to be largerthan an average value lint of current consumed in the internal circuit,till the active mode down converter reaches the operating state, atemporary decrease in the internal power supply voltage Vint can beavoided from occurring.

[0199] For example, in a case where C=10 nF, tact=200 nsec, Vint=2.5Vand Iint=8 mA, if it is set Vstby=2.7, Iav=10 mA and thereby a relationof Iav>Iint can be established.

[0200] Incidentally, while that the internal power supply voltage isincreased to Vstby is unlikely to be preferable in terms of hot electronresistance of MOS transistors which constitute the internal circuit, noproblem associated with hot electron resistance occurs in a case whereno current flows in the internal circuit as in the stand-by mode sincethe hot electron effect is a phenomenon which occurs when a power supplyvoltage is high and a current flows through a MOS transistor.

[0201] A schematic diagram to realize a configuration of the blockdiagram of FIG. 10 is shown in FIG. 12. Circuit blocks of FIG. 12 arerespectively indicated by the same reference numerals as those ofcorresponding blocks of FIG. 10.

[0202] The circuit blocks in the down converter of FIG. 12 comprises:voltage switching circuit 8 constructed of an inverter I11 and NMOS(M11); a PMOS stand-by mode down converter 9 constructed of PMOS (M9), acomparator of a differential amplification type and aresistor circuit inwhich resistors R4, R5 and R6 are serially connected to one another; andan NMOS active mode down converter 10 constructed from voltagegenerating circuit 12 including a voltage limiter 13 and a charge pumpcircuit 14 and NMOS (M10) for voltage decrease.

[0203] The down converter of FIG. 12, as in FIG. 10, further comprises:an enable signal generating section 7 for the active mode downconverter; a stabilization capacitor C3 and an internal circuit 11. Inthe mean time, in FIG. 12, a connection method for the external powersupply voltage Vext to the stand-by and active mode down converters 9and 10 is similar to the cases of the NMOS and PMOS down converters ofFIGS. 29 and 30.

[0204] Then, an operation of the down converter in the sixth embodimentwill be described using FIG. 12. When a semiconductor integrated circuitis in the active mode, an enable signal “H” is input to the inverter I11of the voltage switching circuit 8 and therefore, the gate of NMOS (M11)goes “L.” Accordingly, NMOS (M11) becomes the OFF state and one end of aresistance division type circuit in the stand-by mode down converter 9is grounded through the resistor R6.

[0205] Since, in the stand-by mode down converter 9, a voltage at aconnection point between R4 and R5 is fed back to one of input terminalsof the comparator to the other of whose input terminals a referencevoltage Vref is input and an output terminal of the comparator isconnected to the gate of PMOS (M9) the source of which is connected toVext, the voltage of the connection point is equal to Vref as a resultof a function of the feed-back circuit. Accordingly, the internal powersupply voltage Vint which is output from the drain of PMOS (M9) in theactive mode is expressed by an equation shown in the bottom side of FIG.12 using Vref, resistance values R4, R5 and R6 of the resistors R4, R5and R6.

[0206] On the other hand, when the semiconductor integrated circuit isin the stand-by mode, an enable signal “L” is input to the inverter Illof the voltage switching circuit 8 and therefore, the gate of NMOS (M11)goes “H.” Accordingly, NMOS (M11) becomes the ON state and theintermediate terminal between resistors R5 and R6 of the resistancedivision type circuit in the stand-by mode down converter 9 is groundedthrough NMOS (M11). Therefore, the internal power voltage Vstby isexpressed by an equation shown in the bottom side of FIG. 12 using Vrefand the resistance values R4 and R5 of the resistors R4 and R5.

[0207] In such a manner, a power supply voltage of the internal circuitcan be switched from Vint to Vstby.

[0208] (>Vint) according to the active or stand-by mode of asemiconductor integrated circuit. In the mean time, in FIG. 12, there isshown a state in which the internal power supply voltage is applied tothe internal circuit 11 in the active mode as Vint (VDD).

[0209] Further, while in the active mode of operation, a large currentis constantly supplied to the internal circuit 11 compared with in thestand-by mode and thereby, Vint is necessary to be maintained, a voltageand current in such an active mode are supplied from the active modedown converter 10. The active mode down converter 10 outputs Vint (VDD)to the source of NMOS (M10) by keeping the gate voltage of NMOS (M10) atVint+Vtn (Vtn is a threshold voltage of NMOS) with the voltagegenerating circuit 12 including the limiter 13 and the charge pumpcircuit 14. Further, a supply current in the active mode is secured byincreasing a gate width of NMOS (M10).

[0210] On the other hand, the stand-by down converter 9, as describedabove, includes the comparator and limits a current flowing in theresistance division type circuit including the resistors R4, R5 and R6and the comparator in order to decrease power consumption.

[0211] Then, a PMOS stand-by mode down converter of a seventh embodimentof the present invention will be described using FIGS. 13 and 20 to 22.In the seventh embodiment, descriptions will be given of a configurationof PMOS stand-by mode down converter 9 including a voltage switchingcircuit 8 in the circuit blocks constituting a down converter which havebeen described using FIGS. 10 to 12 together with a variety ofmodifications of the embodiment and accessory circuits thereof. FIG. 13is a diagram showing an example of the circuit configuration of a PMOSstand-by mode down converter including voltage switching circuitaccording to the seventh embodiment.

[0212] The PMOS stand-by mode down converter 9 shown in FIG. 13comprises: a comparator constituted of a differential amplifierincluding MOS transistors M12 to M16; PMOS (M9) whose drain outputs aninternal power supply voltage Vint (VDD); PMOS (M17), whose gate isconnected to Vint through an inverter I12, and which makes a resistancedivision type circuit including resistors R7, R8 and R9 in the ON stateexerting a function of feed-back of Vint (restoration of decrease inVint); PMOS (M19) as voltage switching circuit to whose gate an enablesignal ACTIVEn for an active mode down converter is input throughinverters I13 and I14; and the like.

[0213] An output VBGR of a BGR circuit (reference voltage generatingcircuit) is input to one of input terminals of the comparator as areference voltage and a voltage of a connection node N5 betweenresistors R8 and R9 is input to the other of the input terminals of thecomparator to form a feed-back circuit including the node N5. As thenature of the feed-back circuit, since a voltage of the connection nodeN5 between R8 and R9 becomes VBGR and further ACTIVEn goes “H” in thestand-by mode of a semiconductor integrated circuit, M19 is off and R7is connected to the resistance division type circuit together with M17;while since ACTIVEn goes “L” in the active mode thereof, M19 is on andR7 is set free from the resistance division type circuit together withM17.

[0214] In such a manner, as seen from the equations shown in FIG. 13,Vint is output in the active mode of a semiconductor integrated circuitand Vstby (>Vint) is output in the stand-by mode thereof both as a powersupply voltage VDD of an internal circuit. In the mean time, in FIG. 13,a situation of the circuit is shown in which Vint (VDD) is output to anoutput terminal of the PMOS stand-by mode down converter in the activemode of the semiconductor integrated circuit and Vint is applied tointernal power supply voltage terminals indicated by circles as marks inthe figure. Vint of the terminals are all switched to Vstby in thestand-by mode of the semiconductor integrated circuit.

[0215] Since there is almost no consumption of current in the internalcircuit in the stand-by mode of the semiconductor integrated circuit andfurther neither increase nor decrease in current value occurs, designingof a feed-back system of the PMOS stand-by mode down converter shown inFIG. 13 is not so difficult. In the stand-by mode, a PMOS down converteris easier in estimation of a current than an NMOS down converter whichwill be described below.

[0216] In the circuit shown in FIG. 13, decrease or increase in stand-bycurrent is realized by increase in resistance values of the resistorsR7, R8 and R9, and decrease in magnitude of a current flowing though thecomparator constituted of a differential amplifier by using a value ofan output voltage BIASN of a constant-current source circuit, whichvoltage is supplied to the gate of M12. Further, the reason why thegates of PMOS (M17 and M19) are connected to the external power supplyvoltage Vext through the capacitors C5 and C7 is to shorten a rise timeof the internal power supply voltage Vint or Vstby when a power supplyis turned on.

[0217] That is, when the external power supply voltage is applied, theconstant-current source circuit and the BGR circuit which are driven byVext become the operating states and potentials of BIASN and VBGR whichare outputs of thereof are fixed. At this stage, though the internalpower supply voltage is still not output, a voltage of the node N5 goes“L” since PMOS (M17 and M19) become the OFF state by the capacitors C5and C7, and accordingly, a gate voltage of PMOS (M9) also goes “L.”

[0218] Hence, a power supply line (VDD) of the internal circuit israpidly charged from Vext through PMOS (M9) which is on. When theinternal power supply voltage reaches a value at some level, gatevoltages of PMOS (M17 and M19) are fixed and further the internal powersupply voltage is adjusted to Vint or Vstby by resistance voltagedivision over resistors R7, R8 and R9. In such a manner, the capacitorsC5 and C7 shown in FIG. 13 function as acceleration capacitors.Incidentally, C4 is a stabilization capacitor and C6 is a capacitor forphase compensation.

[0219] In order to accelerate the internal power supply voltage to beincreased, an acceleration circuit as shown in FIG. 20 may be employed,instead of the above described scheme or in combination thereof. Theacceleration means shown in FIG. 20 is constituted of PMOS to whosesource and drain are respectively connected to Vext and Vint, and towhose gate an output “LOWVDDn” of an internal power supply power-ondetecting circuit is connected.

[0220] Characteristics of LOWVDDn are as shown in FIG. 21. If a power-onsignal which is generated from a detecting circuit for the internalpower supply voltage Vint is LOWVDDn, when Vint is increased to reach adetection level V2 set in a power supply voltage detection section (forexample, the reference numeral 1 of FIG. 1), LOWVDDn goes “H” and whenVint is further increased, OUT (an output end of LOWVDDn) of FIG. 9 isincreased together with increase in Vint.

[0221] In FIG. 20, since PMOS (M41) keeps the ON state during the timewhen the internal power supply voltage Vint is lower than a power-ondetection level V2, a power supply line of the internal power supplyvoltage Vint is rapidly charged by the external power supply voltageVext through PMOS (M41). Incidentally, in FIG. 21, while there is aregion where a logical level of the internal power supply power-oncircuit is unstable and a small output signal has a chance to begenerated in the region when Vint is equal to or lower than V1, such anunstable region does not act on the operation of PMOS (M41) in anyadverse way.

[0222] As a modification of a PMOS stand-by mode down converter of theseventh embodiment, a PMOS stand-by mode down converter shown in FIG. 22may be employed. In FIG. 22, NMOS (M42 and M43) are employed instead ofPMOS (M17 and M19) of FIG. 13. Capacitors C15 and C16 are accelerationcapacitance to accelerate increase in the internal power supply voltageVint (VDD) like the capacitors C5 and C7 of FIG. 13.

[0223] Further, while it is different from FIG. 13 that, in FIG. 22,NMOS (M42) is inserted between resistors R8 and R9 and a resistor R8 isinserted between a power supply line (VDD) and NMOS (M43), resistancevalues of R7, R8 and R9 can be the same as those in FIG. 13.

[0224] Then, a concrete circuit configuration of a level shifter 16 ofFIG. 22 is shown in FIG. 16. The level shifter 16 is a latch circuitconstructed of an inverter 122 with Vint as a power supply and aflip-flop of a CMOS type with Vext as a power supply. The reason why thelevel shifter 16 is inserted in FIG. 22 is to avoid decrease inthreshold in voltage transfer by NMOS.

[0225] An NMOS active mode down converter of an eighth embodiment of thepresent invention will be described based on FIGS. 14 to 19. In theeighth embodiment, descriptions will be given of a configuration of anactive mode down converter 10 in the circuit blocks constituting thedown converter which have been described using FIGS. 10 to 12 togetherwith a variety of modifications of the embodiment and accessory circuitsthereof. FIG. 14 is a diagram showing an example of the circuitconfiguration of an NMOS active mode down converter in an eighthembodiment.

[0226] The NMOS active mode down converter shown in FIG. 14 comprises:voltage generating circuit constructed of a voltage limiter 13 and acharge pump circuit 14; and a voltage decrease MOS (M10). The chargepump circuit 14 is provided with two charge pump circuits connected inparallel and an output of an oscillator 15 which is activated byreceiving ACTIVEn is input to the two charge pump circuits through a NORgate G5 and a level shifter 16. Since there arises a risk that when aninternal power supply voltage Vint (VDD) is supplied to the charge pumpcircuits, a large current is consumed in a voltage increase operationand thereby, Vint (VDD) is unstable, an external power supply voltageVext is directly supplied to the charge pump circuits in order to avoidsuch a fluctuation in Vint (VDD). Incidentally, inputting Vext to one ofthe charge pump circuits is effected through an inverter 15.

[0227] An output VDDH0 of the charge pump circuits is given to a voltagelimiter 14 as a voltage VDDH through a resistor R10 and the voltagelimiter 13 compares the voltage VDDH with a voltage limiter referencevoltage VREF′ and transfers a flag signal FLG to one of input terminalsof the NOR gate G5.

[0228] VDDH is input to the gate of voltage decreasing NMOS (M10) whosedrain is connected Vext and Vint (VDD of the internal circuit) is outputfrom the source of voltage decreasing NMOS (M10). A stabilizationcapacitor CDDH is connected to the gate of M10 and further, astabilization capacitor CDD (C3 of FIGS. 10 to 12) of Vint (VDD) isconnected to the source of M10. Incidentally, the voltage limiter 13 andthe charge pump circuits 14 are activated by ACTIVEn.

[0229] When a semiconductor integrated circuit comes to be in the activemode and ACTIVEn goes “L,” the oscillator 15 is in the operating stateand an output pulse φ reaches the charge pump circuits 14 by way of thelevel shifter 16. The reason why the level shifter 16 is inserted isthat a time period required for boosting a voltage is shortened byincreasing an amplitude of the output pulse φ.

[0230] A concrete example of a charge pump circuit 14 is shown in FIG.15. The charge pump circuit 14 comprises: inverters I16 and I19 whichreceive an output pulse φ; and I type NMOS (NMOS whose threshold voltageVtI is as low as about 0.2V) M22 and M24, connected as diodes, to whoseone end output pulses φ and /φ are respectively supplied throughinverters I17 and I18 and a capacitor C8, and inverters I20 and I21 anda capacitor C9. The charge pump circuit 14 outputs VDDH0.

[0231] ACTIVEn is transferred to depletion type NMOS (M20 and M21)through a level shifter 16 which has above been described using FIG. 16and ACTIVEn activates the charge pump circuits 14 in the active mode.

[0232] Since I type NMOS (M26) connected as a diode in FIG. 15 has arectification function in which a current is made to flow in onedirection from Vext to the output end VDDHO, I type NMOS (M26) keepsVDDH (almost equal to VDDH0) of FIG. 14 at Vext-VtI (VtI is a thresholdvoltage of M26) during the stand-by mode in cooperation with M23 and M25and further, functions to keep a boosted voltage of VDDH when a mode ofthe semiconductor integrated circuit is switched from the active mode tothe stand-by mode.

[0233] Hence, in a case where a mode of the semiconductor integratedcircuit is switched from the active mode to the stand-by mode, andfurther, soon reversed to the active mode, a time period required forincrease in voltage of VDDH can be saved. In the mean time, thedepletion type NMOS (M20 and M21) function to keep voltages of nodes N6and N7 at a voltage of Vext during the stand-by mode.

[0234] A circuit configuration of a voltage limiter is shown in FIG.17A. The voltage limiter 13 shown in FIG. 17A comprises: a resistor R11connected between the source of NMOS (M32), connected as a diode, towhose drain VDDH of FIG. 14 is given and the drain of NMOS (M31) towhose gate a signal ACTIVEn is input; a resistance division type circuitconstituted of a variable resistor R12; a comparator of a differentialamplification type to one of whose input terminals a voltage obtained byresistance voltage division of VDDH is input, and to the other of whoseinput terminals a reference voltage Vref′ is input; CMOS inverters (M33and M34) to the gates of which an output terminal of the comparator isconnected; and a NOR gate G6 to one of whose input terminals the outputterminal of the inverters (M33 and M34) is connected.

[0235] A variable resistor R12 functions to adjust a set value of theinternal power supply voltage. A ratio in resistance between theresistors R11 and R12 are only required to be set so that a voltage ofVint′ of FIG. 17 is a set value of the internal power supply voltageVint. A flag signal FLG is output from an output terminal of the NORgate G6.

[0236] In the mean time, an NMOS (M35) is further inserted in the CMOSinverter and the signals ACTIVE and ACTIVEn are respectively input tothe gate of the NMOS (M35) and the other of the input terminals of theNOR gate G6. The signal ACTIVE herein is a signal obtained by invertingthe signal ACTIVEn which goes “L” in the active mode of a semiconductorintegrated circuit with the inverter I23 as shown in FIG. 17 B.

[0237] When VDDH of FIG. 14 reaches a prescribed voltage by the chargepump circuits 14, the voltage limiter shown in FIG. 17 compares avoltage obtained by resistance division of VDDH with Vref′ to detect andoutputs a flag signal FLG shown in FIG. 14 to input to one of the inputterminals of the NOR gate G5. Hence, an output pulse φ of the oscillator15 is not transferred to the charge pump circuits 14 and thereby,increase in VDDH is stopped.

[0238] When VDDH is decreased to lower than a prescribed level, the flagsignal FLG becomes the “L” level and increase in a voltage is restarted.In such a manner, during the time when a semiconductor integratedcircuit is in the active mode, VDDH is kept at a prescribed level. Theresistor R10 in FIG. 14 functions as a filter that a fluctuation inoutput of the charge pump circuits 14 is prevented from being directlytransferred to the voltage limiter 13.

[0239] Since a resistance value of R10 is of the order of 100 Ω and issmall by about two orders of magnitude compared with resistance valuesof the resistors R11 and R12 of the voltage limiter 13 of FIG. 17, aninfluence thereof on a set value of the internal power supply voltageVint can be neglected.

[0240] In FIG. 14, if the resistor R10 is omitted, there arises aproblem associated with an operation as described below. That is, anoutput VDDH0 of the charge pump circuits 14 is fluctuated with anamplitude of about 0.5V by an influence of a pulse signal φ of theoscillator 15. When the VDDH0 is directly input to the voltage limiter13, the flag signal FLG of the voltage limiter 13 is also fluctuated togo “H” or “L” according to the fluctuation in the pulse signal φ. Whilevoltage boosting is also ceased or activated according to thefluctuation, if there arises the duration of voltage boosting due tosuch a noise, a time period required for voltage boosting is extended.If a resistor R10 is provided, a fluctuation of VDDH0 is transferred tothe voltage limiter 13 in a reduced manner and thereby, the duration ofvoltage boosting can be shortened.

[0241] A reference voltage Vref′ which is used in the comparator of thevoltage limiter 13 is generated by a circuit shown in FIG. 18. The Vref′generation circuit of FIG. 18 is a circuit in which Vref′ to provide theinternal power supply voltage Vint, which is higher than in a normaloperation, to the internal circuit in the burn-in test (acurrent-supplied accelerated life test) in order to eliminate earlyfailures of a semiconductor integrated circuit and Vref′ in the normaloperation can be switched therebetween by an internal power supplyburn-in command “EXVDD.”

[0242] The Vref′ generation circuit shown in FIG. 18 comprises: aninverter I24 to which a signal EXVDD is input; a level shifter 16; and aresistance voltage divider including R13 and R14 between PMOS (M36) andNMOS (M37). In the circuit, an intermediate terminal of the resistancevoltage divider is used as an output terminal and the drain of atransfer gate NMOS (M38), to whose gate an output terminal of the levelshifter 16 is connected, and to whose source Vref is input, is connectedto the output terminal of the resistance voltage divider. Incidentally,a stabilization capacitor C10 is connected to the output terminalthereof.

[0243] Further, Vext is connected to the source of PMOS (M36), an outputterminal of the level shifter 16 is connected to the gate thereof, asignal EXVDD is input to the gate of NMOS (M37) and the inverter 124 inparallel, and the source of NMOS (M37) is grounded.

[0244] In such a manner, in a normal operation, when the signal EXVDD isset “L,” Vref (which is obtained by trimming VBGR of FIG. 13) is outputto the Vref′ output without any change therein as shown in the bottomside of FIG. 18 since PMOS (M36) and NMOS (M37) are both off, while NMOS(M38) is on.

[0245] Further, in the bum-in test, if the signal EXVDD is set “H”, anoutput obtained by dividing Vext over resistors R13 and R14 is availablefrom the intermediate terminal of the resistance circuit since PMOS(M36) and NMOS (M37) are both on, while NMOS (M38) is off.

[0246] If the resistance ratio R14/(R13+R14) is set so that VDDH isequal to or higher than Vext+Vt, the output Vint of FIG. 14 is Vint(VDD)=Vext and therefore, the external power supply voltage Vext whichis given to a power supply pad is transferred to a power supply line ofthe internal circuit without any change therein and the burn-in test ofa semiconductor integrated circuit in a current-supplied acceleratedlife test can be performed. Incidentally, differentiation between “L”and “H” of a signal EXVDD is determined by a command “EXVDD” inputexternally.

[0247] When there is NMOS whose threshold voltage is smaller thanVext−Vint in a semiconductor integrated circuit to which the presentinvention is to be applied, an NMOS active mode down converter whichdoes not require any voltage generating circuit comprising a voltagelimiter 13 and a charge pump circuit 14 can be attained by using such aNMOS with the small threshold voltage as a voltage decreasing NMOS.

[0248] In FIG. 19, there is shown an example of a configuration of anNMOS active mode down converter which does not require the voltagegenerating circuit as the modification example of the NMOS active modedown converter of an eighth embodiment.

[0249] An NMOS active mode down converter of FIG. 19 comprises: acomparator to one of whose input terminals Vref′ is input; PMOS (M39),to whose gate the output terminal of the comparator is connected, whosesource is connected to Vext, and to whose drain a resistance divisiontype circuit including resistors R15 and R16 is connected; a feed-backcircuit in which a connection point between R15 and R16 is connected tothe other of the input terminals of the comparator; and voltagedecreasing NMOS (M40) to whose gate VDDH output from the drain of PMOS(M39) is input, whose drain is connected to Vext, and from whose sourcethe internal power supply voltage Vint (VDD) is output.

[0250] In the mean time, stabilization capacitors C12, C13 and C14 arerespectively connected to the feed-back circuit, a VDDH line and a Vint(VDD) output end. Further, C11 is a capacitor for phase compensation. Insuch a manner, if a resistance ratio R15/(R15+R16) is set so that a setvalue of VDDH is equal to or higher than Vint+Vt,′ an output of FIG. 19can be Vint without any charge pump circuit used. Vt′ herein is athreshold voltage of the voltage decreasing NMOS (M40).

[0251] Since, in the NMOS active mode down converter shown in FIG. 19, agate voltage VDHH of the voltage decreasing NMOS (M40) is generatedwithout any charge pump circuit, a time period from the time when asemiconductor integrated circuit goes into the active mode till apotential of VDDH is fixed can be shortened.

[0252] A most crucial difference between an NMOS active mode downconverter of the eighth embodiment and a conventional NMOS downconverter is in a response speed of a system. Since a conventional NMOSdown converter operates a down converter starting from the stand-by modeof a semiconductor integrated circuit, it is required to use a voltagelimiter of a low power consumption. For this reason, a response time ofthe system constructed of a voltage limiter and a charge pump circuit islong. Conventionally, a capacitance value of CDDH (see FIG. 14) has beenset large so that a voltage value of VDDH is not fluctuated even if theresponse speed is low.

[0253] However, since an excessively large area of layout is necessaryif a value of CDDH is large like this, in an NMOS active mode downconverter of the eighth embodiment, the CDDH is designed small and theresponse speed of the system is high so that a time period from when asemiconductor integrated circuit goes into the active mode till avoltage of VDDH is fixed is short.

[0254] Improvement of the response speed of the system is achieved bynot only selecting the resistors R11 and R12 in the voltage limiter 13of FIG. 17 so as to be small in resistance, but increasing a responsespeed of the comparator of a differential amplification type. If theresponse speed of the system is improved like this, current consumptionis increased. However, in the eighth embodiment, since an NMOS activemode down converter is operated only in the active mode, increase inpower consumption is not problematic.

[0255] Further, in the eighth embodiment, in order to decrease a timeperiod till a voltage of VDDH is fixed, not only is a response speed ofa system increased, but a capacitance of CDDH is selected very smallcompared with a conventional case. A capacitance of CDDH is set smallerthan a gate capacitance of each of voltage decreasing NMOS (M10 andM40).

[0256] Since a relative high voltage VDDH is applied to CDDH asdescribed above, CDDH is fabricated using a capacitive device with athick oxide film. For this reason, a layout area for each unitcapacitance of such a capacitive device is large compared with acapacitor of a thin oxide film. Accordingly, that a capacitance of CDDHcan be decreased in the eighth embodiment is a great advantage from theviewpoint of a layout area.

[0257] In the mean time, while when CDDH is small, a fluctuation in VDDHdue to a capacitive coupling and the like is large, no problem arises inthe present invention since a response speed of the voltage generatingcircuit 12 including the voltage limiter 13 and the charge pump circuits14 is improved and therefore, the charge pump circuits 14 quicklyrecovers the original voltage by detecting a fluctuation in the gatevoltage.

[0258] In the sixth to eighth embodiments described above, descriptionsare given of circuit configurations of the down converter in which aPMOS circuit is used in the stand-by mode of a semiconductor integratedcircuit, while an NMOS circuit is used in the active mode thereof. Thefollowing advantages arise by respectively using PMOS and NMOS downconverters in stand-by and active modes:

[0259] (1) since a PMOS down converter is used in the stand-by mode,estimation of a stand-by current becomes easy and the current is alsoeasy to be decreased,

[0260] (2) advantages such as a good stability and ease in designing ofan NMOS down converter are retained, and

[0261] (3) a capacitance of CDDH (a capacitor for stabilization of agate voltage of NMOS) can be decreased compared with a case where anNMOS down converter is, as a single kind, used and thereby, a layoutarea is decreased.

[0262] Further, especially, advantageous points of an NMOS active modedown converter according to the eighth embodiment over a conventionalexample are compiled in the following table. Conventional exampleEmbodiment ^(V)DDH rise time and Long Short response time (−μsec) (−100nsec) ^(C)DDH Large Small (−nF) (−100 PF) Layout area Large area ofSmall area of ^(C)DDH ^(C)DDH

[0263] Then, a ninth embodiment of the present invention will bedescribed based on FIGS. 23 to 25. The ninth embodiment relates to alayout of an NMOS down converter which requires a large gate width.According to this approach, since a distance between a voltagedecreasing NMOS and a peripheral circuit block to which an internalpower supply voltage Vint (hereinafter referred to as VDD) or to part ofwhich an external power supply voltage Vext is supplied can be theminimum, there is no risk that a parasitic resistance arises in thesource of the voltage decreasing NMOS. Further, VDD and Vext can besupplied freely without any restriction on layout of the peripheralcircuit block.

[0264] As described above, while there are available of a PMOS type andof an NMOS type in a down converter which controls VDD, a magnitude ofthe gate width W has to be of the order of 100 mm, since the NMOS downconverter operates a voltage decreasing NMOS in a sub-threshold region.

[0265] In such a manner, since a voltage decreasing NMOS requires alarge layout, a parasitic resistance arises in a power supply line,which is a problem associated with an operation, unless specificcontrivance is made on layout. Further, since two kinds of power supplylines which supply VDD and Vext are arranged on a chip, an overhead inlayout arises.

[0266] In the layout of the ninth embodiment, a down converter is formedin a lower layer of Vext interconnection, PMOS regions of two peripheralcircuit blocks constructed of CMOS are both formed in a lower layer ofVDD interconnection and NMOS regions of the two peripheral circuitblocks are both formed in a lower layer of VSS interconnection (groundline), wherein VDD interconnections are arranged on the both sides of aVext interconnection symmetrically with respect to the Vextinterconnection, and VSS interconnections are arranged on the outside ofthe VDD interconnections symmetrically with respect of the Vextinterconnection, whereby power supply interconnection from the Vextinterconnection and the VDD interconnection of the down converter to thetwo peripheral circuit blocks adjacent thereto can be realized with thesmallest distances.

[0267] With such a structure, since the voltage decreasing NMOS (M10)and the VDD stabilization capacitor CDD of FIG. 14 can be connected tothe two peripheral circuit blocks with the smallest equal distances,control with higher sensitivity can be expected. Further, there can beenjoyed an advantage that supply of Vext and VDD can be effected withoutany restriction on layout.

[0268] A layout of the ninth embodiment is shown in FIG. 23. As shown inthe figure, a Vext interconnection 22 made of a third metal layer isarranged in the center and a VDD interconnection 20 and a VSSinterconnection 19 made of the third metal layer in a similar manner arearranged on both sides of the Vext interconnection 22 symmetrically withrespect thereto. Incidentally, a VDDH interconnection 21 made of thethird metal layer is formed on one side of the Vext interconnection 22.Further, bus lines 18 are arranged along the VSS interconnections 19.

[0269] As shown by an arrow in FIG. 23, an NMOS active mode downconverter of the present invention including a voltage decreasing NMOS(M10) and a VDD stabilization capacitor CDD are formed in a lower layerof the Vext interconnection 22 and an output terminal of the downconverter is connected to the VDDH interconnection and the VDDinterconnections 20.

[0270] The PMOS regions of the two peripheral circuit blocks constructedof CMOS are formed in a lower layer of the VDD interconnections 20arranged in an adjacent manner to both sides of and in symmetry withrespect to the Vext interconnection 22 and the NMOS regions of the twoperipheral circuit regions are formed in a lower layer of the VSSinterconnections 19 arranged on the outside of the VDD interconnectionsand in symmetry with respect to the Vext interconnection 22.

[0271] Then, the layout of a semiconductor integrated circuit of theninth embodiment will be described using FIG. 24. In FIG. 24, anumerical mark 22 which occupies a majority of a central part area is aVext interconnection made of the third metal layer (indicated by M2 inthe figure), 21 is a VDDH interconnection made of the third metal layerand 20 which are respectively shown partly in both sides, upper andlower, are VDD interconnections made of the third metal.

[0272] A common drain 25 of voltage decreasing NMOS (M10) is formed in aregion 23 which is collectively indicated by a bracket in the center ofthe Vext interconnection 22 and gates 29 thereof indicated by hatchingin the figure are formed on both sides of and in symmetry with respectto the common drain 25. Sources 30 of voltage decreasing NMOS (M10) areformed on the outside of and in an adjacent manner to a gate 29. Since agate width of voltage decreasing NMOS (M10) is very large to be 100 mm,two NMOS arranged on both sides of and in symmetry with respect to thecommon drain 25 are in parallel connected and thereby an effective gatewidth is realized twice as wide as actual in this structure.

[0273] The stabilization capacitors CDD for the VDD voltage are formedin regions 24 respectively indicated collectively by brackets ON bothsides of the voltage decreasing NMOS (M10). Each CDD is formed with agate 24 of a MOS structure indicated by hatching in a region 24 as oneelectrode thereof and with a source/drain 33 on both sides of the gate32 short-circuited to each other as the other electrode thereof.

[0274] Connection of a power supply line to voltage decreasing NMOS(M10) and the VDD voltage stabilization capacitor CDD is effected in thefollowing manner. As described above, two voltage decreasing NMOS (M10)23 connected in parallel are arranged in the center of the Vextinterconnection 22 and the Vext interconnection 22 is connected to thedrain 25 of the voltage decreasing NMOS (M10) 23 through a contact hole26 in the center.

[0275] The contact hole 26 herein is used for connection of the thirdmetal layer M2 in which the Vext interconnection 22 is formed between asecond metal layer M1 in which the common drain 25 of the voltagedecreasing NMOSs (M10) 23 is formed and indicated through a mark M2-M1in the bottom side of the figure. Likewise, a contact hole connectingthe third metal layer and a first metal layer therethrough is indicatedby M2-M0, a contact hole connecting the second metal layer and the firstmetal layer therethrough by M1-M0, a contact hole connecting the firstmetal layer and an active region on a silicon substrate therethrough byM0-ACTIVE AREA, which are all shown in the bottom side of FIG. 24.

[0276] A VDDH interconnection 21 made of the third metal layer M2 alongthe Vext interconnection 22 is connected to the second interconnectionlayer M1 through the contact hole 27 and further connected to a gate 29of a voltage decreasing NMOS (M10) 23 through the contact hole 28.

[0277] Further, a voltage VDD of a source 30 of a voltage decreasingNMOS (M10) is led out by the first metal layer M0 and connected to agate 32 of a MOS structure constituting the stabilization capacitor CDD24 through a contact hole 31.

[0278] The voltage VDD is further led out by the first metal layer M0 tothe both sides of the Vext interconnection and connected to a VDDinterconnection made of the third metal layer through a contact hole 35.The contact hole 35 is a contact hole connecting M2-M0 therethrough.

[0279] The source/drain 33 of a stabilization capacitor CDD isshort-circuited by the second metal layer M1, led out up to a VDDinterconnection and further connected to a VDD interconnection made ofthe third metal layer (not shown).

[0280] Further, the Vext interconnection is connected to the secondmetal layer M1 by the drain 25 of voltage decreasing NMOS (M10) 23 andthereafter, led out to both sides 34 of the Vext interconnection 22through the second metal layer M1. With such a structure, the VDDvoltage is output on the VDD interconnections 20 made of the third metallayer on both side of the Vext interconnection 22 and the Vext voltageis output by an interconnection 34 made of the second metal layer M1 inparallel to the VDD interconnection 20. That is, the VDD interconnection20 and the Vext interconnection 34 which is branched from the Vextinterconnection 22 are doubly arranged on both sides of the Vextinterconnection 22.

[0281] Since a PMOS region of a peripheral circuit block is arrangedadjacent to the Vext interconnection 22, a VDD interconnection 20 ledout from the source 30 of a voltage decreasing NMOS (M10) 23 can be usedas the power supply line for the PMOS region without any change.Further, the Vext voltage can easily be supplied to peripheral circuitssuch as a charge pump circuit which require the Vext voltage byextending the interconnection 34 made of the second metal layer M1.

[0282]FIG. 25 is a conceptual illustration showing a layout example of asemiconductor integrated circuit of the ninth embodiment. Thesemiconductor integrated circuit shown in FIG. 25 comprises: a memorycell array 37 formed on a semiconductor chip 36; down converters 38; andperipheral logic circuits 39. Since peripheral logic circuits 39 arearranged on both sides of a down converter 38 symmetrically with respectthereto, and VDD and Vext are supplied from a site very close to a downconverter 38, a length of power supply interconnection can extremely bereduced compared with that of a conventional semiconductor integratedcircuit.

[0283] Since interconnection resistance added to the sources of voltagedecreasing NMOS (M10) can be the minimum according to the layout of theninth embodiment, precise control of the VDD voltage can be achieved.Further, since stabilization capacitors CDD for the VDD voltage can beconnected to peripheral logic circuit blocks in a uniform manner interms of interconnection resistance, the stabilization capacitors CDDcan effectively used in a uniform manner even when a power supplycurrent is locally increased according to an operating state.

[0284] While, in the embodiments described above, descriptions are givenof power supply voltage detection circuits of a semiconductor integratedcircuit which generates power-on signals at different detection levels;down converter of a semiconductor integrated circuit, which comprisecircuits respectively for the stand-by and active modes, and whereby nodecrease in voltage occurs even immediately after switching between theoperating modes; and related layouts, it is to be understood that thepresent invention is not limited to the above described embodiments, butthe embodiments can be modified or altered in various ways without anydeparture from the scope of the present invention as hereinafterclaimed.

[0285] Effects of the present invention will be described. According tothe present invention, as described above as well, there can be provideda semiconductor integrated circuit which includes a power supply voltagedetection circuit which respectively generates power-on signals when apower supply voltage is increased to be equal to or higher than aprescribed voltage V1 and when a power supply voltage is decreased to beequal to or lower than a prescribed voltage V2 that is different fromthe V1. Especially, when down converter is used, a power supply voltagedetection circuit which satisfies a condition V1>V2 has an effect not todetect instantaneous decrease in power supply voltage. Further, a powersupply voltage detection circuit which is in a condition V1<V2 has aneffect that decrease in power supply voltage is immediately detected anda prescribed operation of recovery is surely performed.

[0286] Further, according to the present invention, in a semiconductorintegrated circuit including stand-by and active mode down converters,an effect is obtained that a temporary decrease in internal power supplyvoltage immediately after transition from the stand-by mode to theactive mode can be suppressed.

[0287] Further, according to the present invention, there can beprovided down converter exerting an excellent effect on realization ofeasy designing and decreasing a stand-by current by selectively usingNMOS and PMOS down converters therebetween according an operating state.Further, in a case where the down converter is applied to a non-volatilememory, there is another effect to greatly decrease a layout area.

[0288] Further, according to a layout method for a semiconductorintegrated circuit of the present invention, since a distance betweendown converter and a peripheral circuit block to which a VDD voltage issupplied can be minimum, there arises no risk that a parasiticresistance is added to a source of the voltage-decreasing NMOS. Thereby,down converter with high controllability can be realized.

[0289] Further, a VDD interconnection and a Vext interconnection areformed in a two layer structure by forming a branched interconnection ofthe Vext interconnection above a down converter in a lower layer of theVDD interconnection whose VDD voltage is output from the down converterand thereby, the VDD and the Vext can both be supplied to a peripheralcircuit block with the minimum distances, so that there can be providedan effect that a necessary power supply line to a peripheral circuitblock can be selected only in interconnection layers and thereby, layoutof a peripheral circuit block in a chip can freely be designed.

[0290] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

1. A semiconductor integrated circuit comprising: a down converter whichgenerates an internal power supply voltage on a semiconductor chip froman external power supply voltage which is supplied from the outside ofthe semiconductor chip; and a charge pump circuit which generates anboosted voltage on the semiconductor chip from the external power supplyvoltage.